tc90a58f TOSHIBA Semiconductor CORPORATION, tc90a58f Datasheet - Page 18

• Manufacturer Part Number: tc90a58f
• Description: 3-channel Ad Converter
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Sub-Address 03H
Sub-Address 04H
·
·
·
·
·
·
·
·
·
Default
Default
Name
Name
HVSEL65: Changes the HD and VD output timing in relation to EAV.
INTER: Sets the VD output to be once or twice per frame (Note4).
VNSOFF: Enables/Disables VD input.
VDPO: Sets the VD input polarity.
VDDIRECT: Selects VD input.
HDPO: Sets the HD input polarity.
HDDIRECT: Selects HD input.
HRTMG10: Sets the number of samples per 1H. Sets in combination with HRTMG9~HRTMG2 in
HRTMG9~HRTMG2: Sets the number of samples per 1H. This setting works in combination
Note4: A frame consists of 525 lines for NTSC; 625 lines for PAL.
Bit
Bit
0 (default): HD and VD output timing is the same as EAV.
1: HD and VD output timing is delayed in relation to EAV by +32 clocks for NTSC and by +24
0 (default): Outputs VD for each field.
1: Outputs VD per frame.
0 (default): Enables VD input.
0 (default): Same polarity
0 (default): Identifies input pulses of 8 clocks or more as VD input.
1: Identifies input pulses of 1 clock or more as VD input.
0 (default): Same polarity
0 (default): Identifies input pulses of 8 clocks or more as HD input.
1: Identifies input pulses of 1 clock or more as HD input.
clocks for PAL.
(Enabled only when VRNMOD = 1)
HVSEL65
HRTMG9
7 (MSB)
7 (MSB)
Sub-Address 04H and HRTMG1~HRTMG0 in Sub-Address 05H.
0
1
with HRTMG10 in Sub-Address 03H and HRTMG1~HRTMG0 in Sub-Address
05H.
HRTMG8
INTER
6
0
6
0
VNSOFF
HRTMG7
5
0
5
1
1: Opposite polarity
1: Opposite polarity
1: Disables VD input.
18
HRTMG6
VDPO
4
0
4
0
VDDIRECT
HRTMG5
3
0
3
1
HRTMG4
HDPO
2
0
2
1
HDDIRECT
HRTMG3
1
0
1
0
TC90A58F
2002-02-06
HRTMG10
HRTMG2
0 (LSB)
0 (LSB)
1
0