tc90a58f TOSHIBA Semiconductor CORPORATION, tc90a58f Datasheet - Page 4

• Manufacturer Part Number: tc90a58f
• Description: 3-channel Ad Converter
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Pin Functions
No.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
1
2
3
4
5
6
7
8
9
Pin Name
DACOUT
EXTCLK
VRM_Q
DVDDP
VDOUT
HDOUT
VRB_Q
VRT_Q
APCLK
DVSSP
BOUT0
BOUT1
BOUT2
VRM_I
VRB_I
AIN_Q
AVDD
VRT_I
AVDD
PVDD
HREF
DVDD
DVSS
AVSS
AVSS
PVSS
AIN_I
HDIN
VDIN
BIAS
BFIL
SDA
VB1
LFIL
SCL
I/O
I/O
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
Bias pin (for AD)
AD reference voltage (middle)
AD reference voltage (bottom)
Analog power supply
AD input
Analog GND
AD reference voltage (top)
Analog pin (for testing)
Analog pin (for testing)
AD reference voltage (middle)
AD reference voltage (bottom)
Analog power supply
AD input
Analog GND
AD reference voltage (top)
HPLL power supply
Clock output
HPLL GND
HPLL filter
For stabilization
Digital power supply
External clock input
Digital GND
HD input
VD input
HPLL pin
I
I
VD output
HD output
Digital power supply
Digital GND
-/B/-OUTPUT
-/B/-OUTPUT
-/B/-OUTPUT
2
2
C bus data
C bus clock
Function
4
Ground to AVSS (pin 6) via 0.1-mF capacitor.
Same as above
Same as above
Connect 0.47-mF capacitor and 20-W resistor.
Ground to AVSS (pin 6) via 0.1-mF capacitor.
For testing purposes
Ground to AVSS (pin 14) via 0.1-mF capacitor.
Ground to AVSS (pin 14) via 0.1-mF capacitor.
Ground to AVSS (pin 14) via 0.1-mF capacitor.
Connect 0.47-mF capacitor and 20-W resistor.
Ground to AVSS (pin 14) via 0.1-mF capacitor.
Outputs clock with amplitude of 1 V
corresponding I
When I
fixed to L.
Connecta 1-mF capacitor and a 1.0-kW resistor.
Connect other end of capacitor as near to PVSS as possible.
Also connect 0.01-mF capacitor in parallel with above capacitor
and resistor.
Connect 0.01-mF capacitor.
For HPLL
Used as clock input pin in External Clock Mode.
When built-in HPLL is used, set input to H or fix input to L.
For HPLL
5-V withstanding voltage
5-V withstanding voltage
Input for external HPLL reference signal
Phase is compared on rising edge.
5-V withstanding voltage
5-V withstanding voltage
Outputs vertical sync signal pulse.
Pulse polarity can be set using I
Outputs horizontal sync signal pulse.
Pulse polarity can be set using I
Internal, for output PAD
Internal, for output PAD
2
C bus register settings are default values, outputs are
2
C bus register setting.
Notes
¾
¾
¾
¾
¾
¾
¾
¾
¾
2
2
C bus register.
C bus register.
p-p
according to
TC90A58F
2002-02-06