tc90a58f TOSHIBA Semiconductor CORPORATION, tc90a58f Datasheet - Page 9

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tc90a58f

Manufacturer Part Number
tc90a58f
Description
3-channel Ad Converter
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
VD
(INPUT, odd field)
HD (INPUT)
MCK (APCLK)
(29.862 MHz)
HDOUT
VDOUT
5. HD Output
6. VD Output
Odd field
(pin 29).
HDOUT. The timing can be selected in the I
also be generated internally.
Select internal generation using the VRNMOD bit in the I
HD
(INPUT)
MCK (APCLK)
(29.862 MHz)
HDOUT
The output timing and width of HDOUT (pin 30) can be set in the I
The HD signal input from the HDIN (pin 24) can pass through unaltered and be output from HDOUT.
In this case, the HDOUT output is delayed by 15 clocks from the HDIN input.
Through Mode can be set using the HDSELB bit in the I
The VD signal output from the VDIN (pin 24) can pass through unaltered and be output from VDOUT
There are two output timings: output delayed by 15 clocks from VDIN or output at the same timing as
Timing: HDSTA10~HDSTA5 in Sub-Address 05H and HDSTA4~HDSTA0 in Sub-Address 06H
Output width: HDPW10~HDPW8 in Sub-Address 06H and HDPW7~HDPW0 in Sub-Address 07H
Variable (set using I
Within 15 clocks
2
C bus register)
Figure 3 HDOUT Timing Chart
Figure 4 VDOUT Timing Chart
(set in I
HD output width
2
C bus register)
When VDSEL = 0, VDSOFF = 0 and VRNMOD = 0, VD input from VDIN is
output, delayed by 15 clocks.
With all other settings, VDOUT changes with the same timing as HDOUT.
2
Variable (set using I
C bus register VDOSEL Sub-Address 09H. The VD signal can
9
(set in I
HD output timing
1/2H
2
2
C bus register Sub-Address 02H.
C bus register Sub-Address 00H.
2
2
C bus register)
C bus register)
2
C bus registers (see figure below).
TC90A58F
2002-02-06

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