tc90a58f TOSHIBA Semiconductor CORPORATION, tc90a58f Datasheet - Page 19

• Manufacturer Part Number: tc90a58f
• Description: 3-channel Ad Converter
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Sub-Address 05H
Sub-Address 06H
Sub-Address 07H
Sub-Address 08H
·
·
·
·
·
·
·
Default
Default
Default
Default
Name
Name
Name
Name
HRTMG1~HRTMG0: Sets the number of samples per 1H. This setting works in combination with the
HDSTA10~HDSTA5: Sets the HD output timing. This setting works in combination with the setting
HDSTA4~HDSTA0: Sets the HD output timing. This setting works in combination with the setting of
HDPW10~HDPW8: Sets the HD width. This setting works in combination with the setting of HDPW7
HDPW7~HDPW0: Sets the HD width. This setting works in combination with the setting of HDPW10
IHVD: Sets whether the I
VRTMG9~VRTMG3: Sets the number of lines per frame. Enabled only when VLINSEL in
Bit
Bit
Bit
Bit
0 (default): I
1: I
2
C bus data is updated at VD cycle.
HRTMG1
HDSTA4
7 (MSB)
7 (MSB)
7 (MSB)
7 (MSB)
HDPW7
IHVD
1
1
1
0
2
C bus data is updated continuously.
~HDPW8 in Sub-Address 06H.
HDSTA10~HDSTA5 in Sub-Address 05H.
~HDPW0 in Sub-Address 07H.
Sub-Address 00H = 1. This setting works in combination with the setting of
VRTMG2~VRTMG0 in Sub-Address 09H.
settings of HRTMG10 in Sub-Address 03H and HRTMG9~HRTMG2 in
Sub-Address 04H.
of HDSTA4~HDSTA0 in Sub-Address 06H.
HRTMG0
VRTMG9
HDSTA3
HDPW6
2
6
1
6
0
6
0
6
1
C bus data is updated continuously or at the VD cycle.
HDSTA10
VRTMG8
HDSTA2
HDPW5
5
0
5
0
5
0
5
0
19
VRTMG7
HDSTA9
HDSTA1
HDPW4
4
0
4
0
4
0
4
0
VRTMG6
HDSTA8
HDSTA0
HDPW3
3
0
3
0
3
0
3
0
HDPW10
VRTMG5
HDSTA7
HDPW2
2
0
2
0
2
0
2
0
VRTMG4
HDSTA6
HDPW9
HDPW1
1
0
1
0
1
0
1
0
TC90A58F
2002-02-06
VRTMG3
HDSTA5
HDPW8
HDPW0
0 (LSB)
0 (LSB)
0 (LSB)
0 (LSB)
0
0
0
1