xr16l2751im Exar Corporation, xr16l2751im Datasheet - Page 10

• Manufacturer Part Number: xr16l2751im
• Description: 2.25v To 5.5v Duart With 64-byte Fifo And Powersave
• Manufacturer: Exar Corporation

XR16L2751
2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE
Beyond the general 16C2550 features and capabilities, the 2751 offers enhanced feature registers (EFR, Xon/
Xoff 1, Xon/Xoff 2, FCTR, TRG, EMSR, FC) that provide automatic RTS and CTS hardware flow control, Xon/
Xoff software flow control, automatic RS-485 half-duplex direction output enable/disable, FIFO trigger level
control and FIFO level counters. All the register functions are discussed in full detail later in
UART INTERNAL REGISTERS” on page
The device does not support direct memory access. The DMA Mode (a legacy term) in this document doesn’t
mean “direct memory access” but refers to data block transfer operation. The DMA mode affects the state of
the RXRDY# A/B and TXRDY# A/B output pins. The transmit and receive FIFO trigger levels provide additional
flexibility to the user for block mode operation. The LSR bits 5-6 provide an indication when the transmitter is
empty or has an empty location(s) for more data. The user can optionally operate the transmit and receive
FIFO in the DMA mode (FCR bit-3 = 1). When the transmit and receive FIFO are enabled and the DMA mode
is disabled (FCR bit-3 = 0), the 2751 is placed in single-character mode for data transmit or receive operation.
When DMA mode is enabled (FCR bit-3 = 1), the user takes advantage of block mode operation by loading or
unloading the FIFO in a block sequence determined by the programmed trigger level. In this mode, the 2751
sets the TXRDY# pin when the transmit FIFO becomes full, and sets the RXRDY# pin when the receive FIFO
becomes empty. The following table shows their behavior. Also see Figures
The INTA and INTB interrupt output changes according to the operating mode and enhanced features setup.
Table 4 and 5
through 25.
2.7
2.8
RXRDY# A/B LOW = 1 byte.
TXRDY# A/B LOW = THR empty.
INTA/B Pin
INTA/B Pin
INTA/B Pin
P
INS
DMA Mode
INTA and INTB Outputs
HIGH = no data.
HIGH = byte in THR.
summarize the operating behavior for the transmitter and receiver. Also see Figures
A
(FIFO D
LOW = no data
HIGH = 1 byte
UTO
FCR
M
YES
NO
T
ODE
RS485
ABLE
BIT
(FIFO D
ISABLED
T
FCR B
-0=0
ABLE
T
3: TXRDY#
ABLE
LOW = a byte in THR
HIGH = THR empty
LOW = a byte in THR
HIGH = transmitter empty
)
IT
ISABLED
4: INTA
-0 = 0
5: INTA
LOW = at least 1 byte in FIFO.
HIGH = FIFO empty.
LOW = FIFO empty.
HIGH = at least 1 byte in FIFO.
(FIFO D
FCR B
)
(DMA M
AND
AND
AND
22.
FCR B
IT
ISABLED
INTB P
RXRDY# O
-0 = 0
LOW = FIFO below trigger level
HIGH = FIFO above trigger level
INTB P
ODE
IT
)
D
-3 = 0
INS
ISABLED
10
IN
O
UTPUTS IN
O
PERATION FOR
LOW = FIFO above trigger level
HIGH = FIFO below trigger level or FIFO empty
LOW = FIFO above trigger level
HIGH = FIFO below trigger level or transmitter empty
PERATION
FCR B
)
IT
HIGH to LOW transition when FIFO reaches the
trigger level, or time-out occurs.
LOW to HIGH transition when FIFO empties.
LOW = FIFO has at least 1 empty location.
HIGH = FIFO is full.
-0=1 (FIFO E
FIFO
F
FCR B
OR
(FIFO E
FCR B
T
AND
RANSMITTER
R
ECEIVER
IT
20
DMA M
-0 = 1 (FIFO E
(DMA M
IT
NABLED
NABLED
through 25.
-0 = 1
FCR B
ODE
)
ODE
)
IT
-3 = 1
E
NABLED
NABLED
xr
“Section 3.0,
)
)
REV. 1.2.2
20