xr16l2751im Exar Corporation, xr16l2751im Datasheet - Page 34

• Manufacturer Part Number: xr16l2751im
• Description: 2.25v To 5.5v Duart With 64-byte Fifo And Powersave
• Manufacturer: Exar Corporation

XR16L2751
2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE
MSR[7]: CD Input Status
Normally this bit is the complement of the CD# input. In the loopback mode this bit is equivalent to bit-3 in the
MCR register. The CD# input may be used as a general purpose input when the modem interface is not used.
This is a 8-bit general purpose register for the user to store temporary data. The content of this register is
preserved during sleep mode but becomes 0xFF (default) after a reset or a power off-on cycle.
This register replaces SPR (during a Write) and is accessible only when FCTR[6] = 1.
EMSR[1:0]: Receive/Transmit FIFO Count (Write-Only)
When Scratchpad Swap (FCTR[6]) is asserted, EMSR bits 1-0 controls what mode the FIFO Level Counter is
operating in.
During Alternate RX/TX FIFO Counter Mode, the first value read after EMSR bits 1-0 have been asserted will
always be the RX FIFO Counter. The second value read will correspond with the TX FIFO Counter. The next
value will be the RX FIFO Counter again, then the TX FIFO Counter and so on and so forth.
EMSR[2]: Reserved
EMSR[3]: Automatic RS485 Half-Duplex Control Output Inversion
•
•
4.10
4.11
Logic 0 = RTS# output is LOW during TX and HIGH during RX (default, compatible with 16C2850).
Logic 1 = RTS# output is HIGH during TX and LOW during RX.
Scratchpad Register (SPR) - Read/Write
Enhanced Mode Select Register (EMSR)
FCTR[6]
0
1
1
1
1
T
ABLE
EMSR[1] EMSR[0] Scratchpad is
13: S
X
0
0
1
1
CRATCHPAD
X
0
1
0
1
34
S
Scratchpad
RX FIFO Counter Mode
TX FIFO Counter Mode
RX FIFO Counter Mode
Alternate RX/TX FIFO
Counter Mode
WAP
S
ELECTION
xr
REV. 1.2.2