xr16l2751im Exar Corporation, xr16l2751im Datasheet - Page 24

• Manufacturer Part Number: xr16l2751im
• Description: 2.25v To 5.5v Duart With 64-byte Fifo And Powersave
• Manufacturer: Exar Corporation

XR16L2751
2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE
SEE”RECEIVER” ON PAGE 14.
SEE”TRANSMITTER” ON PAGE 13.
The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status
and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR).
When the receive FIFO (FCR BIT-0 = 1) and receive interrupts (IER BIT-0 = 1) are enabled, the RHR interrupts
(see ISR bits 2 and 3) status will reflect the following:
A. The receive data available interrupts are issued to the host when the FIFO has reached the programmed
4.0 INTERNAL REGISTER DESCRIPTIONS
4.1
4.2
4.3
4.3.1
A
A2-A0
DDRESS
0 0 0
0 0 0
0 0 1
0 0 0
0 0 1
0 0 0
0 0 1
0 1 0
1 0 0
1 0 1
1 1 0
1 1 1
trigger level. It will be cleared when the FIFO drops below the programmed trigger level.
T
Receive Holding Register (RHR) - Read- Only
Transmit Holding Register (THR) - Write-Only
Interrupt Enable Register (IER) - Read/Write
ABLE
IER versus Receive FIFO Interrupt Mode Operation
XOFF1 RD/WR
XOFF2 RD/WR
DREV
XON1 RD/WR
XON2 RD/WR
FCTR RD/WR
N
DVID
DLM
TRG
EFR
R
DLL
FC
AME
EG
9: INTERNAL REGISTERS DESCRIPTION.
RD/WR
RD/WR
RD/WR
R
W
WR
RD
RD
RD
EAD
RITE
/
Enable
RX/TX
Mode
B
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Auto
Bit-7
Bit-7
Bit-7
Bit-7
CTS
IT
0
-7
SCPAD
Enable
Swap
B
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Auto
RTS
Bit-6
Bit-6
Bit-6
Bit-6
IT
0
-6
Baud Rate Generator Divisor
Enhanced Registers
Special
Select
Table
B
Char
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Bit-1
Bit-5
Bit-5
Bit-5
Bit-5
Trig
IT
0
-5
24
FCR[5:4]
MCR[7:5
Enable
Table
B
[7:4],
[5:4],
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-0
Bit-4
Bit-4
Bit-4
Bit-4
Trig
IER
ISR
IT
0
,
]
-4
S
HADED BITS ARE ENABLED WHEN
Direction
Control
RS485
B
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Auto
Soft-
ware
Flow
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Cntl
IT
1
-3
RX IR
B
Input
ware
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Soft-
Flow
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Cntl
Inv.
IT
0
-2
B
Soft-
ware
Flow
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Auto
RTS
Hyst
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Cntl
IT
1
-1
EFR B
B
ware
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Auto
Hyst
Bit-0
Soft-
Flow
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
RTS
Cntl
xr
IT
0
-0
IT
-4=1
LCR ≠ 0xBF
LCR ≠ 0xBF
LCR=0
DLM=0x00
DLL=0x00
C
LCR[7]=1
LCR[7]=1
REV. 1.2.2
OMMENT
X
BF