xr16c864iq Exar Corporation, xr16c864iq Datasheet - Page 12

• Manufacturer Part Number: xr16c864iq
• Description: Quad Uart With Rx/tx Fifo Counters And 128-byte Fifo
• Manufacturer: Exar Corporation

XR16C864
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
In this document, Direct Memory Access will not be referred to by its acronym (DMA) to avoid confusion with
DMA Mode (a legacy term) that refers to data block transfer operation. Direct Memory Access mode is enabled
via EMSR bits 2 and 3. The Direct Memory Access transaction is controlled through the RXDRQ [A-D],
TXDRQ [A-D], DACK [A-D], AEN and TC pins.
The DMA Mode (a legacy term) in this document doesn’t mean “direct memory access” but refers to data block
transfer operation. (Since the 864 also supports Direct Memory Access, “Direct Memory Access” will be used
instead of “DMA” when explaining Direct Memory Access.) The DMA mode affects the state of the RXRDY# A-
D and TXRDY# A-D output pins. The transmit and receive FIFO trigger levels provide additional flexibility to the
user for block mode operation. The LSR bits 5-6 provide an indication when the transmitter is empty or has an
empty location(s) for more data. The user can optionally operate the transmit and receive FIFO in the DMA
mode (FCR bit-3=1). When the transmit and receive FIFO are enabled and the DMA mode is disabled (FCR
bit-3 = 0), the 864 is placed in single-character mode for data transmit or receive operation. When DMA mode
is enabled (FCR bit-3 = 1), the user takes advantage of block mode operation by loading or unloading the FIFO
in a block sequence determined by the programmed trigger level. The following table show their behavior. Also
see
The 864 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for all four UART sections in the
device. The CPU data bus does not require this clock for bus operation. The crystal oscillator provides a
system clock to the Baud Rate Generators (BRG) section found in each of the UART. XTAL1 is the input to the
oscillator or external clock buffer input with XTAL2 pin being the output. For programming details, see
“Programmable Baud Rate Generator.”
F
The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant,
fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100ppm frequency
tolerance) connected externally between the XTAL1 and XTAL2 pins (see
2.8
2.9
2.10
IGURE
RXRDY#
TXRDY#
Figure 19
P
INS
4. T
Direct Memory Access
DMA Mode
Crystal Oscillator or External Clock Input
T
YPICAL OSCILATOR CONNECTIONSL
ABLE
through 23.
0 = 1 byte
1 = no data
0 = THR empty
1 = byte in THR
(FIFO D
5: TXRDY#
FCR
BIT
ISABLED
-0=0
AND
)
RXRDY# O
0 = at least 1 byte in FIFO
1 = FIFO empty
0 = FIFO empty
1 = at least 1 byte in FIFO
(DMA Mode Disabled)
2 2-4 7 pF
X T A L 1
FCR Bit-3 = 0
C 1
UTPUTS IN
R =3 0 0 K to 40 0 K
1 4.7 45 6
M H z
12
FIFO
FCR B
2 2-4 7 pF
X T A L 2
AND
C 2
IT
-0=1 (FIFO E
DMA M
1 to 0 transition when FIFO reaches the trigger
level, or timeout occurs.
0 to 1 transition when FIFO empties.
0 = FIFO has at least 1 empty location.
1 = FIFO is full.
ODE FOR
Figure
(DMA Mode Enabled)
NABLED
FCR Bit-3 = 1
4). Typical standard crystal
C
HANNELS
)
áç
áç
áç
áç
A-D
REV. 2.0.1