xr16c864iq Exar Corporation, xr16c864iq Datasheet - Page 17

• Manufacturer Part Number: xr16c864iq
• Description: Quad Uart With Rx/tx Fifo Counters And 128-byte Fifo
• Manufacturer: Exar Corporation

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REV. 2.0.1
When software flow control is enabled
characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) match the
programmed values, the 864 will halt transmission as soon as the current character has completed
transmission. When a match occurs, the Xoff (if enabled via IER bit-5) flag will be set and the interrupt output
pin will be activated. Following a suspension due to a match of the Xoff character, the 864 will monitor the
receive data stream for a match to the Xon-1,2 character. If a match is found, the 864 will resume operation
and clear the flags (ISR bit-4).
Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to a logic 0. Following reset the user
can write any Xon/Xoff value desired for software flow control. Different conditions can be set to detect Xon/
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F
2.17
IGURE
Enable CTS interrupt through IER bit-7 (after setting EFR bit-4). The UART issues an interrupt when the
CTS# pin is de-asserted (logic 1): ISR bit-5 will be set to 1, and UART will suspend transmission as soon as
the stop bit of the character in process is shifted out. Transmission is resumed after the CTS# input is re-
asserted (logic 0), indicating more data may be sent.
The local UART (UARTA) starts data transfer by asserting RTSA# (1). RTSA# is normally connected to CTSB# (2) of
remote UART (UARTB). CTSB# allows its transmitter to send data (3). TXB data arrives and fills UARTA receive FIFO
(4). When RXA data fills up to its receive FIFO trigger level, UARTA activates its RXA data ready interrupt (5) and con-
tinues to receive and put data into its FIFO. If interrupt service latency is long and data is not being unloaded, UARTA
monitors its receive data fill level to match the upper threshold of RTS delay and de-assert RTSA# (6). CTSB# follows
(7) and request UARTB transmitter to suspend data transfer. UARTB stops or finishes sending the data bits in its trans-
mit shift register (8). When receive FIFO data in UARTA is unloaded to match the lower threshold of RTS delay (9),
UARTA re-asserts RTSA# (10), CTSB# recognizes the change (11) and restarts its transmitter and data flow again until
next receive FIFO trigger (12). This same event applies to the reverse direction when UARTA sends data to UARTB
with RTSB# and CTSA# controlling the data flow.
10. A
Auto Xon/Xoff (Software) Flow Control
UTO
(RXA FIFO
CTSB#
RXA FIFO
Interrupt)
RTSA#
TXB
INTA
Trigger Reached
RTS
Receiver FIFO
Trigger Level
Local UART
Transmitter
Auto CTS
Auto RTS
UARTA
Monitor
AND
Data Starts
Receive
Data
CTS F
Assert RTS# to Begin
1
2
Transmission
Trigger Level
3
LOW
4
RX FIFO
RTSA#
TXA
CTSA#
RXA
ON
C
(See Table
ON
ONTROL
5
O
PERATION
7
Threshold
17), the 864 compares one or two sequential receive data
RTS High
17
6
8
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
OFF
Suspend
OFF
RTSB#
CTSB#
Threshold
RTS Low
RXB
TXB
Restart
9
10
11
Trigger Reached
Remote UART
ON
Trigger Level
Receiver FIFO
12
Auto CTS
Transmitter
Auto RTS
UARTB
Monitor
ON
Trigger Level
RX FIFO
R T S C T S 1
XR16C864