xr16c864iq Exar Corporation, xr16c864iq Datasheet - Page 34

• Manufacturer Part Number: xr16c864iq
• Description: Quad Uart With Rx/tx Fifo Counters And 128-byte Fifo
• Manufacturer: Exar Corporation

XR16C864
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
MSR[7]: CD Input Status
CD# (active high, logical 1). Normally this bit is the compliment of the CD# input. In the loopback mode this bit
is equivalent to bit-3 in the MCR register. The CD# input may be used as a general purpose input when the
modem interface is not used.
This is a 8-bit general purpose register for the user to store temporary data. The content of this register is
preserved during sleep mode but becomes 0xFF (default) after a reset or a power off-on cycle.
This register replaces SPR (during a Write) and is accessible only when FCTR[6] = 1.
EMSR[1:0]: Receive/Transmit FIFO Count (Write-Only)
When Scratchpad Swap (FCTR[6]) is asserted, EMSR bits 1-0 controls what mode the FIFO Level Counter is
operating in.
During Alternate RX/TX FIFO Counter Mode, the first value read after EMSR bits 1-0 have been asserted will
always be the RX FIFO Counter. The second value read will correspond with the TX FIFO Counter. The next
value will be the RX FIFO Counter again, then the TX FIFO Counter and so on and so forth.
EMSR[2]: Transmit Direct Memory Access Request Enable
Logic 0 = Normal.
Logic 1 = Enable TX Direct Memory Access Request. See DACK, TC, AEN, TXDRQ and RXDRQ pin
descriptions for details.
EMSR[3]: Receive Direct Memory Access Request Enable
Logic 0 = Normal.
Logic 1 = Enable RX Direct Memory Access Request. See DACK, TC, AEN, TXDRQ and RXDRQ pin
descriptions for details.
4.10
4.11
Scratch Pad Register (SPR) - Read/Write
Enhanced Mode Select Register (EMSR)
FCTR[6]
0
1
1
1
1
EMSR[1]
X
0
0
1
1
T
ABLE
14: S
EMSR[0]
CRATCHPAD
X
0
1
0
1
34
S
Scratchpad
RX FIFO Counter Mode
TX FIFO Counter Mode
RX FIFO Counter Mode
Alternate RX/TX FIFO Counter Mode
Scratchpad is
WAP
S
ELECTION
áç
áç
áç
áç
REV. 2.0.1