xr16c864iq Exar Corporation, xr16c864iq Datasheet - Page 51

• Manufacturer Part Number: xr16c864iq
• Description: Quad Uart With Rx/tx Fifo Counters And 128-byte Fifo
• Manufacturer: Exar Corporation

áç
áç
REV. 2.0.1
ELECTRICAL CHARACTERISTICS................................................................................ 40
T
áç
áç
ABLE OF
A
T
DC E
AC E
TA=0
P
R
YPICAL PACKAGE THERMAL RESISTANCE DATA
BSOLUTE
ACKAGE
4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY ............................................................................... 26
4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY ..................................................................................... 27
4.6 LINE CONTROL REGISTER (LCR) - READ/WRITE ..................................................................................... 29
4.7 MODEM CONTROL REGISTER (MCR) OR GENERAL PURPOSE OUTPUTS CONTROL - READ/WRITE 31
4.8 LINE STATUS REGISTER (LSR) - READ ONLY ........................................................................................... 32
4.9 MODEM STATUS REGISTER (MSR) - READ ONLY .................................................................................... 33
4.10 SCRATCH PAD REGISTER (SPR) - READ/WRITE .................................................................................... 34
4.11 ENHANCED MODE SELECT REGISTER (EMSR) ...................................................................................... 34
4.12 FIFO LEVEL REGISTER (FLVL) - READ-ONLY ......................................................................................... 35
4.13 BAUD RATE GENERATOR REGISTERS (DLL AND DLM) - READ/WRITE .............................................. 35
4.14 DEVICE IDENTIFICATION REGISTER (DVID) - READ ONLY .................................................................... 35
4.15 DEVICE REVISION REGISTER (DREV) - READ ONLY .............................................................................. 35
4.16 TRIGGER LEVEL (TRG) - WRITE-ONLY ..................................................................................................... 35
4.17 FIFO DATA COUNT REGISTER (FC) - READ-ONLY ................................................................................. 36
4.18
4.19 ENHANCED FEATURE REGISTER (EFR) - READ/WRITE ........................................................................ 36
4.20 SOFTWARE FLOW CONTROL REGISTERS (XOFF1, XOFF2, XON1, XON2) - READ/WRITE ................ 38
4.21 FIFO STATUS REGISTER (FSTAT) - READ/WRITE ................................................................................... 38
EVISION
T
T
T
T
T
T
T
T
T
F
F
F
F
F
F
F
F
F
F
F
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
IGURE
IGURE
IGURE
IGURE
IGURE
IGURE
IGURE
IGURE
IGURE
IGURE
IGURE
LECTRICAL
LECTRICAL
O TO
4.3.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION ............................................................................. 25
4.3.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION................................................................ 25
4.4.1 INTERRUPT GENERATION: ...................................................................................................................................... 26
4.4.2 INTERRUPT CLEARING: ........................................................................................................................................... 26
FEATURE CONTROL REGISTER (FCTR) - READ/WRITE ....................................................................... 36
10: I
11: T
12: P
13: INT O
14: S
15: A
16: T
17: S
18: UART RESET CONDITIONS FOR CHANNELS A-D ................................................................................................. 39
13. C
14. M
15. 16 M
16. 16 M
17. 68 M
18. 68 M
19. R
20. T
21. R
22. R
23. T
H
D
C
M
70
ISTORY
IMENSIONS
ONTENTS
AXIMUM
NTERRUPT
O
RANSMIT AND
ARITY SELECTION
CRATCHPAD
UTO
RIGGER
OFTWARE
RANSMIT
RANSMIT
LOCK
ECEIVE
ECEIVE
ECEIVE
ODEM
C (-40
C
C
RTS H
UTPUT
ODE
ODE
ODE
ODE
HARACTERISTICS
HARACTERISTICS
...................................................................................................................................... 49
T
I
T
IMING
NPUT
R
R
R
R
ABLE
(I
(I
(M
(M
O TO
S
F
R
R
EADY
EADY
EADY
................................................................................................................................. 48
NTEL
NTEL
ATINGS
OURCE AND
LOW
M
YSTERESIS
EADY
EADY
OTOROLA
OTOROLA
........................................................................................................... 1
S
R
ODES
/O
WAP
............................................................................................................................................................. 42
S
ECEIVE
) D
) D
UTPUT
& I
& I
& I
ELECT
C
+85
........................................................................................................................................................ 30
& I
& I
ONTROL
S
ATA
ATA
..................................................................................................................................................... 31
NTERRUPT
NTERRUPT
NTERRUPT
ELECTION
..................................................................................................................... 40
NTERRUPT
NTERRUPT
O
) D
) D
FIFO T
............................................................................................................................................... 35
............................................................................................................................................... 36
T
B
B
C
P
IMING
ATA
ATA
US
US
RIORITY
.............................................................................................................. 40
.............................................................................................................. 41
FOR INDUSTRIAL GRADE PACKAGE
F
UNCTIONS
R
W
B
B
EAD
T
T
T
RIGGER
.................................................................................................................................... 34
RITE
F
US
US
IMING
T
IMING
IMING
T
OR
IMING
IMING
L
R
W
T
EVEL
T
C
EAD
IMING FOR
RITE
IMING FOR
HANNELS
[N
[FIFO M
[FIFO M
........................................................................................................................ 37
L
[N
[FIFO M
EVEL
..................................................................................................................... 27
T
ON
(M
T
ON
IMING FOR
IMING FOR
-FIFO M
-FIFO M
ARGIN OF ERROR
S
ODE
ODE
C
A-D .................................................................................................... 42
ELECTION
C
ODE
HANNELS
HANNELS
2
, DMA D
, DMA E
ODE
, DMA M
C
ODE
C
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
HANNELS
HANNELS
]
............................................................................................ 29
FOR
]
A-D ................................................................................... 43
FOR
A-D .................................................................................. 43
NABLED
ISABLED
ODE
C
C
HANNELS
A-D........................................................................... 44
A-D ......................................................................... 44
HANNELS
: ± 15%) ................................................ 40
D
]
]
ISABLED
), V
FOR
FOR
CC IS
C
A-D ............................................................ 45
C
A-D .......................................................... 45
HANNELS
HANNELS
]
FOR
2.97
C
HANNELS
A-D............................................ 46
A-D........................................... 46
TO
5.5V ........................ 41
A-D .............................. 47
XR16C864