xr16c864iq Exar Corporation, xr16c864iq Datasheet - Page 5

• Manufacturer Part Number: xr16c864iq
• Description: Quad Uart With Rx/tx Fifo Counters And 128-byte Fifo
• Manufacturer: Exar Corporation

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REV. 2.0.1
Pin Description
MODEM OR SERIAL I/O INTERFACE
RXDRQA
RXDRQB
RXDRQC
RXDRQD
TXDRQA
TXDRQB
TXDRQC
TXDRQD
DACKA
DACKB
DACKC
DACKD
RTSA#
RTSB#
RTSC#
RTSD#
CTSA#
CTSB#
CTSC#
CTSD#
IRTXA
IRTXB
IRTXC
IRTXD
N
RXC
RXD
AEN
TXA
TXB
TXC
TXD
RXA
RXB
TC
AME
100-QFP
P
100
54
26
55
77
25
56
81
31
50
82
14
16
65
67
24
57
75
97
34
47
85
11
19
62
70
22
59
73
IN
27
4
5
6
8
#
T
YPE
O
O
O
O
O
I
I
I
I
I
Direct Memory Access Terminal Count. A high pulse terminates a Direct Memory Access
transaction. If Direct Memory Access is not used, this input should be connected to GND.
Address Enable for Direct Memory Access. A high at this input indicates a valid Direct
Memory Access cycle. See DACK pin descriptions below for Direct Memory Access cycle
description. If Direct Memory Access is not used, this input should be connected to GND.
Direct Memory Access Acknowledge. Direct Memory Access cycle will start processing
when CPU/Host sets this input low and AEN high. All writes will be to the TX FIFO and all
reads will be from the RX FIFO. A0-A2 and CS# A-D will be ignored. If Direct Memory
Access is not used, these inputs should be connected to VCC.
Transmit Direct Memory Access Request. A transmit empty request is indicated by a high
level on TXDRQ. The TXDRQ line is held high until either TC pulses or the TX FIFO is
filled above its trigger level. Transmit Direct Memory Access Request is enabled by set-
ting EMSR register bit-2 = 1. If Direct Memory Access is not used, leave these outputs
unconnected.
Receive Direct Memory Access Request. A Receive ready request is indicated by a high
level on RXDRQ. The RXDRQ line is held high until either TC pulses or the RX FIFO is
emptied. Receive Direct Memory Access Request is enabled by setting EMSR register
bit-3 = 1. If Direct Memory Access is not used, leave these outputs unconnected.
UART channels A-D Transmit Data and infrared transmit data. Standard transmit and
receive interface is enabled when MCR[6] = 0. In this mode, the TX signal will be a logic
1 during reset, or idle (no data). Infrared IrDA transmit and receive interface is enabled
when MCR[6] = 1. In the Infrared mode, the inactive state (no data) for the Infrared
encoder/decoder interface is a logic 0.
UART channels A-D Infrared Transmit Data. The inactive state (no data) for the Infrared
encoder/decoder interface is a logic 0. Regardless of the logic state of MCR bit-6, this pin
will be operating in the Infrared mode.
UART channels A-D Receive Data or infrared receive data. Normal receive data input
must idle at logic 1 condition. The infrared receiver pulses typically idles at logic 0 but can
be inverted by software control prior going in to the decoder, see FCTR[2].
UART channels A-D Request-to-Send (active low) or general purpose output. This output
must be asserted prior to using auto RTS flow control, see EFR[6], MCR[1], FCTR[1:0],
EMSR[5:4] and IER[6]. Also see
unconnected.
UART channels A-D Clear-to-Send (active low) or general purpose input. It can be used
for auto CTS flow control, see EFR[7], and IER[7]. Also see
should be connected to VCC when not used.
5
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
Figure
D
ESCRIPTION
10. If these outputs are not used, leave them
Figure
10. These inputs
XR16C864