xr17c152im Exar Corporation, xr17c152im Datasheet - Page 22

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xr17c152im

Manufacturer Part Number
xr17c152im
Description
5v Pci Bus Dual Uart
Manufacturer
Exar Corporation
Datasheet

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XR17C152
5V PCI BUS DUAL UART
The XR17C152 also provides the same RX FIFO data along with the LSR status information of each byte side-
by-side, at locations 0x180 (channel 0) and 0x380 (channel 1). The entire RX data along with the status can be
downloaded in a single PCI Burst Read operation of 32 DWORD reads. The Status and Data bytes must be
read in 16 or 32 bits format to maintain data integrity. The following tables show this clearly.
The TX FIFO data (up to the maximum 64 bytes) can be loaded in a single burst 32-bit write operation
(maximum 16 DWORD writes) at memory locations 0x100 (channel 0) and 0x300 (channel 1).
3.1.2
3.1.3
Data Bit-31
Data Bit-31
WITH LSR
Read n+0 to n+1
Read n+2 to n+3
Write n+0 to n+3
Write n+4 to n+7
PCI Bus
R
W
PCI Bus
EAD
B7 B6 B5 B4 B3 B2 B1 B0
RITE
B7 B6 B5 B4 B3 B2 B1 B0
Receive Data Byte n+1
Etc.
RX FIFO,
Etc
Receive Data Byte n+3
TX FIFO
Special Rx FIFO Data Unloading at locations 0x180 (channel 0) and 0x380 (channel 1)
Tx FIFO Data Loading at locations 0x100 (channel 0) and 0x300 (channel 1)
E
RRORS
Channel 0 to 1 ReceiveData in 32-bit alignment through the Configuration Register Address
Channel 0 to 1 Receive Data with Line Status Register in a 32-bit alignment through
FIFO Data n+1
FIFO Data n+3
FIFO Data n+3
FIFO Data n+7
B
B
B7 B6 B5 B4 B3 B2 B1 B0
YTE
YTE
B7 B6 B5 B4 B3 B2 B1 B0
Line Status Register n+1
3
3
Receive Data Byte n+2
the Configuration Register Address 0x0180 and 0x0380
FIFO Data n+2
FIFO Data n+6
0x0100 and 0x0300
LSR n+1
LSR n+3
B
B
YTE
YTE
22
B7 B6 B5 B4 B3 B2 B1 B0
B7 B6 B5 B4 B3 B2 B1 B0
2
2
Receive Data Byte n+0
Receive Data Byte n+1
FIFO Data n+0
FIFO Data n+2
FIFO Data n+1
FIFO Data n+5
B
B
YTE
YTE
1
1
B7 B6 B5 B4 B3 B2 B1 B0
B7 B6 B5 B4 B3 B2 B1 B0
Line Status Register n+0
Receive Data Byte n+0
áç
áç
áç
áç
FIFO Data n+0
FIFO Data n+4
LSR n+0
LSR n+2
B
B
YTE
YTE
REV. 1.2.0
Data Bit-0
Data Bit-0
0
0
PCI Bus
PCI Bus

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