xr17c152im Exar Corporation, xr17c152im Datasheet - Page 29

• Manufacturer Part Number: xr17c152im
• Description: 5v Pci Bus Dual Uart
• Manufacturer: Exar Corporation

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REV. 1.2.0
Two interrupts associated with auto RTS/CTS and DTR/DSR flow control have been added to give indication
when RTS#/DTR# pin or CTS#/DSR# pin are de-asserted during operation. These interrupts are enabled by:
Automatic hardware flow control is selected by setting bits 6 (RTS) and 7 (CTS) of the EFR register to logic 1.
If CTS# pin transitions from LOW to HIGH indicating a flow control request, ISR bit-5 will be set to logic 1, (if
enabled via IER bit 6-7), and the UART will suspend TX transmissions as soon as the stop bit of the character
in process is shifted out. Transmission is resumed after the CTS# input returns LOW, indicating more data may
be sent.
F
IGURE
The local UART (UARTA) starts data transfer by asserting -RTSA# (1). RTSA# is normally connected to CTSB# (2) of
remote UART (UARTB). CTSB# allows its transmitter to send data (3). TXB data arrives and fills UARTA receive FIFO
(4). When RXA data fills up to its receive FIFO trigger level, UARTA activates its RXA data ready interrupt (5) and con-
tinues to receive and put data into its FIFO. If interrupt service latency is long and data is not being unloaded, UARTA
monitors its receive data fill level to match the upper threshold of RTS delay and de-assert RTSA# (6). CTSB# follows
(7) and request UARTB transmitter to suspend data transfer. UARTB stops or finishes sending the data bits in its trans-
mit shift register (8). When receive FIFO data in UARTA is unloaded to match the lower threshold of RTS delay (9),
UARTA re-asserts RTSA# (10), CTSB# recognizes the change (11) and restarts its transmitter and data flow again until
next receive FIFO trigger (12). This same event applies to the reverse direction when UARTA sends data to UARTB
with RTSB# and CTSA# controlling the data flow.
Setting EFR bit-4 =1 to enable the shaded register bits
Setting IER bit-7 will enable the CTS#/DSR# interrupt when these pins are de-asserted. The selection of
CTS# or DSR# is selected via MCR bit-2. See
Setting IER bit-6 will enable the RTS#/DTR# interrupt when these pins are de-asserted. The selection of
RTS# or DTR# is selected via MCR bit-2. See
14. A
(RXA FIFO
CTSB#
RXA FIFO
Interrupt)
RTSA#
TXB
INTA
Trigger Reached
UTO
Receiver FIFO
Trigger Level
Local UART
Transmitter
Auto CTS
Auto RTS
UARTA
Monitor
RTS/DTR
Data Starts
Receive
Data
Assert RTS# to Begin
1
AND
2
Transmission
Trigger Level
3
4
RX FIFO
CTS/DSR F
RTSA#
TXA
CTSA#
RXA
ON
ON
LOW
5
Table 10
Table 10
C
7
Threshold
RTS High
ONTROL
29
6
8
above for complete details.
above for complete details.
OFF
Suspend
O
OFF
PERATION
RTSB#
CTSB#
RTS Low
Threshold
RXB
TXB
Restart
9
10
11
Trigger Reached
ON
Remote UART
Trigger Level
Receiver FIFO
12
5V PCI BUS DUAL UART
Auto CTS
Transmitter
Auto RTS
UARTB
Monitor
ON
Trigger Level
RX FIFO
R T S C T S 1
XR17C152