xr17c152im Exar Corporation, xr17c152im Datasheet - Page 6

• Manufacturer Part Number: xr17c152im
• Description: 5v Pci Bus Dual Uart
• Manufacturer: Exar Corporation

XR17C152
5V PCI BUS DUAL UART
FUNCTIONAL DESCRIPTION
The XR17C152 (152) integrates the functions of 2 enhanced 16550 UARTs with the PCI Local Bus interface
and a non-volatile memory interface for PCI bus’s plug-and-play auto-configuration, a 16-bit timer/counter, 8
multi-purpose inputs/outputs, and an on-chip oscillator. The PCI local bus is a synchronous timing bus where
all bus transactions are associated to the bus clock of up to 33 MHz. The 152 supports 32-bit wide read and
write data transfer operations including data burst mode through the PCI Local Bus interface. Read and write
data operations may be in byte, word or double-word (DWORD) format. The data transfer rate in a DWORD
operation is 4 times faster than the single byte operation with 8-bit ISA bus. A single 32-bit interrupt status reg-
ister provides interrupts status for both UARTs, timer/counter, multipurpose inputs/outputs, and a special sleep
wake up indicator. There are three sets of registers in the device. First, the PCI local bus configuration regis-
ters for PCI auto configuration. A set of device configuration registers for overall control, 32-bit wide transmit
and receive data transfer, and monitoring of the 2 UART channels. Lastly, each UART channel has its own
16550 UART compatible configuration register set for individual channel control, status, and byte wide data
transfer. See electrical characteristics table for more details.
Each UART has the fifth generation (5G) register set, 64-byte FIFOs, automatic RTS/CTS or DTR/DSR hard-
ware flow control with hysteresis control, automatic Xon/Xoff and special character software flow control, pro-
grammable transmit and receive FIFO trigger level, FIFO level counters, infrared encoder and decoder (IrDA
ver 1.0), programmable baud rate generator with a prescaler of 1X or 4X, and data rate up to 3 Mbps. The
XR17C152 bus timing and drive capability meets the PCI local bus specification revision 2.2 for 5 volt 33 MHz
operation over the temperature range. For a pin-to-pin compatible part that can operate at 3.3V, see the
XR17D152.
PCI L
This is the host interface and it meets the PCI Local Bus Specification revision 2.2. The PCI local bus
operations are synchronous meaning each transaction is associated to the bus clock. The XR17C152 can
operate with the bus clock of up to a 33.34 MHz. Data transfers operation can be formatted in 8-bit, 16-bit, 24-
bit or 32-bit wide. With 32-bit data operations, it pushes the data transfer rate on the bus up to 132 MByte/sec.
This increases the overall system’s communication performance up to 16 times better than the 8-bit ISA bus.
See PCI local bus specification revision 2.2 for bus operation details.
PCI L
A set of PCI local bus configuration space register is provided. These registers provide the PCI local bus
operating system with the card’s vendor ID, device ID, sub-vendor ID, product model number, and resources
and capabilities. The PCI local bus operating system collects this data from all the cards on the bus during the
auto configuration phase that follows immediately after a power up or system reset/reboot. After it has sorted
out all devices on the bus, it defines and download the operating conditions to the cards. One of the definitions
is the base address loaded into the Base Address Register (BAR) where the card will be operating in the PCI
local bus memory space.
EEPROM I
An external 93C46 EEPROM is only used to store the vendor’s ID and model number, and the sub-vendor’s ID
and product model number. This information is only used with the plug-and-play auto configuration of the PCI
local bus. These data provide automatic hardware installation onto the PCI bus. The EEPROM interface
consists of 4 signals, EEDI, EEDO, EECS, and EECK. The EEPROM is not needed when auto configuration is
not required in the application. However, if your design requires non-volatile memory for other purpose. It is
possible to store and retrieve data on the EEPROM through a special PCI device configuration register. See
application note DAN112 for its programming details.
OCAL
OCAL
NTERFACE
B
B
US
US
I
C
NTERFACE
ONFIGURATION
S
PACE
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EGISTERS
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REV. 1.2.0