sc16c852 NXP Semiconductors, sc16c852 Datasheet - Page 18

• Manufacturer Part Number: sc16c852
• Description: 2.5 V To 3.3 V Dual Uart, 5 Mbit/s Max. With 128-byte Fifos, Infrared Irda And 16 Mode Or 68 Mode Bus Interface
• Manufacturer: NXP Semiconductors

NXP Semiconductors
SC16C852_1
Product data sheet
6.10 DMA operation
6.11 Loopback mode
The SC16C852 FIFO trigger level provides additional flexibility to the user for block mode
operation. The user can optionally operate the transmit and receive FIFOs in the DMA
mode (FCR[3]). The DMA mode affects the state of the RXRDYA/RXRDYB and
TXRDYA/TXRDYB output pins.
Table 8.
[1]
Table 9.
[1]
The internal loopback capability allows on-board diagnostics. In the Loopback mode, the
normal modem interface pins are disconnected and reconfigured for loopback internally
(see
In the Loopback mode, the transmitter output (TX) and the receiver input (RX) are
disconnected from their associated interface pins, and instead are connected together
internally. The CTS, DSR, CD, and RI are disconnected from their normal modem control
input pins, and instead are connected internally to RTS, DTR, MCR[3] (OP2A/OP2B) and
MCR[2] (OP1A/OP1B). Loopback test data is entered into the transmit holding register via
the user data bus interface, D[7:0]. The transmit UART serializes the data and passes the
serial data to the receive UART via the internal loopback connection. The receive UART
converts the serial data back into parallel data that is then made available at the user data
interface D[7:0]. The user optionally compares the received data to the initial transmitted
data for verifying error-free operation of the UART TX/RX circuits.
In this mode, the interrupt pin is 3-stated, therefore, the software must use the polling
method (see
Non-DMA mode
1 = FIFO empty
0 = at least 1 byte in FIFO
Non-DMA mode
1 = at least 1 byte in FIFO
0 = FIFO empty
Receive FIFO becomes full at 32 bytes when in normal mode. When TXINTLVL or RXINTLVL or FLWCNTH
or FLWCNTL contains any value other than 0x00 (extended mode), then the receive FIFO becomes full at
128 bytes.
Transmit FIFO becomes full at 32 bytes when in normal mode. When TXINTLVL or RXINTLVL or
FLWCNTH or FLWCNTL contains any value other than 0x00 (extended mode), then the transmit FIFO
becomes full at 128 bytes.
Figure
Effect of DMA mode on state of RXRDYA/RXRDYB pin
Effect of DMA mode on state of TXRDYA/TXRDYB pin
8). MCR[3:0] register bits are used for controlling loopback diagnostic testing.
Section
7.2.2) to send and receive data.
Rev. 01 — 31 August 2009
Dual UART with 128-byte FIFOs and IrDA encoder/decoder
DMA mode
0-to-1 transition when FIFO empties
1-to-0 transition when FIFO reaches trigger level, or time-out
occurs
DMA mode
0-to-1 transition when FIFO becomes full
1-to-0 transition when FIFO has at least one empty location
Table 8
[1]
and
Table 9
show this.
[1]
SC16C852
© NXP B.V. 2009. All rights reserved.
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