sc16c852 NXP Semiconductors, sc16c852 Datasheet - Page 13

• Manufacturer Part Number: sc16c852
• Description: 2.5 V To 3.3 V Dual Uart, 5 Mbit/s Max. With 128-byte Fifos, Infrared Irda And 16 Mode Or 68 Mode Bus Interface
• Manufacturer: NXP Semiconductors

NXP Semiconductors
SC16C852_1
Product data sheet
6.4.1 32-byte FIFO mode
6.4.2 128-byte FIFO mode
6.4 FIFO operation
6.5 Hardware flow control
When all four of these registers (TXINTLVL, RXINTLVL, FLWCNTH, FLWCNTL) in the
‘First extra feature register set’ are empty (0x00) the transmit and receive trigger levels are
set by FCR[7:4]. In this mode the transmit and receive trigger levels are backward
compatible to the SC16C652B (see
transmit and receive data FIFOs are enabled by the FIFO Control Register bit 0 (FCR[0]).
It should be noted that the user can set the transmit trigger levels by writing to the FCR,
but activation will not take place until EFR[4] is set to a logic 1. The receiver FIFO section
includes a time-out function to ensure data is delivered to the external CPU (see
Section
Table 6.
When either TXINTLVL, RXINTLVL, FLWCNTH or FLWCNTL in the ‘first extra feature
register set’ contains any value other than 0x00, the transmit and receive trigger levels are
set by TXINTLVL and RXINTLVL registers. TXINTLVL sets the trigger levels for the
transmit FIFO, and the transmit trigger levels can be set to any value between 1 and 128
with granularity of 1. RXINTLVL sets the trigger levels for the receive FIFO, the receive
trigger levels can be set to any value between 1 and 128 with granularity of 1.
When the effective FIFO size changes (that is, when FCR[0] toggles or when the
combined content of TXINTLVL, RXINTLVL, FLWCNTH and FLWCNTL changes between
equal and unequal to 0x00), both RX FIFO and TX FIFO will be reset (data in the FIFO will
be lost).
When automatic hardware flow control is enabled, the SC16C852 monitors the
CTSA/CTSB pin for a remote buffer overflow indication and controls the RTSA/RTSB pin
for local buffer overflows. Automatic hardware flow control is selected by setting EFR[6]
(RTS) and EFR[7] (CTS) to a logic 1. If CTS transitions from a logic 0 to a logic 1
indicating a flow control request, ISR[5] will be set to a logic 1 (if enabled via IER[7:6]),
and the SC16C852 will suspend TX transmissions as soon as the stop bit of the character
in process is shifted out. Transmission is resumed after the CTSx input returns to a
logic 0, indicating more data may be sent.
When AFCR1[2] is set to logic 1 then the function of CTSA/CTSB pin is mapped to the
DSRA/DSRB pin, and the function of RTSA/RTSB is mapped to DTRA/DTRB pin. DSRx
and DTRx pins will behave as described above for CTS and RTS.
FCR[7:6]
00
01
10
11
6.8). Please refer to
Interrupt trigger level and flow control mechanism
FCR[5:4]
00
01
10
11
Rev. 01 — 31 August 2009
INTA/INTB pin activation
RX
8
16
24
28
Dual UART with 128-byte FIFOs and IrDA encoder/decoder
Table 13
TX
16
8
24
30
Table
and
6), and the FIFO sizes are 32 entries. The
Table 14
Negate RTS or
send Xoff
8
16
24
28
for the setting of FCR[7:4].
SC16C852
Assert RTS or
send Xon
0
7
15
23
© NXP B.V. 2009. All rights reserved.
13 of 60