sc16c852 NXP Semiconductors, sc16c852 Datasheet - Page 29

• Manufacturer Part Number: sc16c852
• Description: 2.5 V To 3.3 V Dual Uart, 5 Mbit/s Max. With 128-byte Fifos, Infrared Irda And 16 Mode Or 68 Mode Bus Interface
• Manufacturer: NXP Semiconductors

NXP Semiconductors
SC16C852_1
Product data sheet
7.4 Interrupt Status Register (ISR)
The SC16C852 provides six levels of prioritized interrupts to minimize external software
interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status
bits. Performing a read cycle on the ISR will provide the user with the highest pending
interrupt level to be serviced. No other interrupts are acknowledged until the pending
interrupt is serviced. A lower level interrupt may be seen after servicing the higher level
interrupt and re-reading the interrupt status bits.
data values (bits 5:0) for the six prioritized interrupt levels and the interrupt sources
associated with each of these interrupt levels.
Table 15.
Table 16.
Priority
level
1
2
2
3
4
5
6
Bit
7:6
5:4
3:1
0
Symbol
ISR[7:6]
ISR[5:4]
ISR[3:1]
ISR[0]
ISR[5]
0
0
0
0
0
0
1
Interrupt source
Interrupt Status Register bits description
ISR[4]
0
0
0
0
0
1
0
Description
FIFOs enabled. These bits are set to a logic 0 when the FIFOs are not being
used in the non-FIFO mode. They are set to a logic 1 when the FIFOs are
enabled in the SC16C852 mode.
INT priority bits 4:3. These bits are enabled when EFR[4] is set to a logic 1.
ISR[4] indicates that matching Xoff character(s) have been detected. ISR[5]
indicates that CTS, RTS have been generated. Note that once set to a
logic 1, the ISR[4] bit will stay a logic 1 until Xon character(s) are received.
INT priority bits 2:0. These bits indicate the source for a pending interrupt at
interrupt priority levels 1, 2, and 3 (see
INT status.
Rev. 01 — 31 August 2009
logic 0 or cleared = default condition
logic 0 or cleared = default condition
logic 0 or cleared = default condition
logic 0 = an interrupt is pending and the ISR contents may be used as a
pointer to the appropriate interrupt service routine
logic 1 = no interrupt pending (normal default condition)
ISR[3]
0
0
1
0
0
0
0
Dual UART with 128-byte FIFOs and IrDA encoder/decoder
ISR[2]
1
1
1
0
0
0
0
ISR[1]
1
0
0
1
0
0
0
Table 15 “Interrupt source”
ISR[0]
0
0
0
0
0
0
0
Table
Source of the interrupt
LSR (Receiver Line Status
Register)
RXRDY (Received Data Ready)
RXRDY (Receive Data time-out)
TXRDY (Transmitter Holding
Register Empty)
MSR (Modem Status Register)
RXRDY (Received Xoff signal)/
Special character
CTS, RTS change of state
15).
SC16C852
© NXP B.V. 2009. All rights reserved.
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