a3pn010 Actel Corporation, a3pn010 Datasheet

a3pn010

Manufacturer Part Number

a3pn010

Description

Proasic 3 Nano Flash Fpgas

Manufacturer

Actel Corporation

Datasheet

1.A3PN010.pdf (144 pages)

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November 2009

Radiation-Tolerant ProASIC3 Low-Power Space-

Flight Flash FPGAs

with Flash*Freeze Technology

Features and Benefits

MIL-STD-883 Class B Qualified Packaging

Low Power

Radiation Tolerant

High Capacity

Reprogrammable Flash Technology

High Performance

In-System Programming (ISP) and Security

High-Performance Routing Hierarchy

Table I-1 • Radiation-Tolerant (RT) ProASIC3 Low-Power Space-Flight FPGAs

RT ProASIC3 Devices

System Gates

VersaTiles (D-flip-flops)

RAM kbits (1,024 bits)

4,608-Bit Blocks

FlashROM Bits

Secure (AES) ISP

Integrated PLL in CCCs

VersaNet Globals

I/O Banks

Maximum User I/Os

Package Pins

• Ceramic Column Grid Array with Six Sigma Copper-

• Land Grid Array

• Dramatic Reduction in Dynamic and Static Power

• 1.2 V to 1.5 V Core and I/O Voltage Support for Low

• Low Power Consumption in Flash*Freeze Mode Enables

• Supports Single-Voltage System Operation

• Low-Impedance Switches

• 15 krad Total Ionizing Dose (TID)

• Wafer-Lot-Specific TID Reports

• 600 k to 3 M System Gates

• Up to 504 kbits of True Dual-Port SRAM

• Up to 620 User I/Os

• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS

• Live-at-Power-Up (LAPU) Level 0 Support

• Single-Chip Solution

• Retains Programmed Design when Powered Off

• 350 MHz (1.5 V) and 250 MHz (1.2 V) System Performance

• 3.3 V, 66 MHz, 66-Bit PCI (1.5 V); 66 MHz, 32-Bit PCI (1.2 V)

• Secure ISP Using On-Chip 128-Bit Advanced Encryption

• FlashLock

• Segmented, Hierarchical Routing and Clock Structure

CCGA/LGA

CQFP

Wrapped Lead-Tin Columns

Power

Instantaneous

Flash*Freeze Mode

Process

Standard (AES) Decryption via JTAG (IEEE 1532–compliant)

to Secure FPGA Contents

Entry

Exit

From

Low-Power

RT3PE600L

CG/LG484

13,824

CQ256

600 k

108

270

Yes

1 k

Advanced and Pro (Professional) I/Os

Clock Conditioning Circuit (CCC) and PLL

SRAMs and FIFOs

• High-Performance, Low-Skew Global Network

• Architecture Supports Ultra-High Utilization

• 700 Mbps DDR, LVDS-Capable I/Os

• 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage

• Bank-Selectable I/O Voltages—up to 8 Banks per Chip

• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /

• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and M-LVDS

• Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL

• I/O Registers on Input, Output, and Enable Paths

• Hot-Swappable and Cold-Sparing I/Os

• Programmable Output Slew Rate and Drive Strength

• Programmable Input Delay (RT3PE3000L only)

• Schmitt

• Weak Pull-Up/-Down

• IEEE 1149.1 (JTAG) Boundary Scan Test

• Pin-Compatible Packages across the Radiation-Tolerant

• Six CCC Blocks, All with Integrated PLL (RT ProASIC3)

• Configurable

• Wide Input Frequency Range 1.5 MHz to 250 MHz (1.2 V

• Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4,

• True Dual-Port SRAM (except ×18)

• 24 SRAM and FIFO Blocks with Synchronous Operation:

Operation

2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X, and

LVCMOS 2.5 V / 5.0 V Input

2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3

Class I and II (RT3PE3000L only)

(RT3PE3000L)

ProASIC

Capabilities, and External Feedback

systems) and 350 MHz (1.5 V systems)

×9, and ×18 organizations available)

– 250 MHz: For 1.2 V Systems

– 350 MHz: For 1.5 V Systems

3 Family

Trigger

Phase

Option

Shift,

CG/LG484, CG/LG896

RT3PE3000L

75,264

CQ256

Multiply/Divide,

3 M

504

112

620

Yes

1 k

Single-Ended

Advance v0.2

Inputs

Delay

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