a3pn010 Actel Corporation, a3pn010 Datasheet - Page 7

• Manufacturer Part Number: a3pn010
• Description: Proasic 3 Nano Flash Fpgas
• Manufacturer: Actel Corporation

Figure 1-1 • RT ProASIC3 Device Architecture Overview
Decryption*
ISP AES
Advanced Flash Technology
The RT ProASIC3 family offers many benefits, including nonvolatility and reprogrammability,
through an advanced flash-based, 130-nm LVCMOS process with 7 layers of metal. Standard CMOS
design techniques are used to implement logic and control functions. The combination of fine
granularity, enhanced flexible routing resources, and abundant flash switches allows for very high
logic utilization without compromising device routability or performance. Logic functions within
the device are interconnected through a four-level routing hierarchy.
Advanced Architecture
The proprietary RT ProASIC3 architecture provides granularity comparable to standard-cell ASICs.
The RT ProASIC3 device consists of five distinct and programmable architectural features
(Figure
The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input
logic function, a D-flip-flop (with or without enable), or a latch by programming the appropriate
flash switch interconnections. The versatility of the RT ProASIC3 core tile, as either a three-input
lookup table (LUT) equivalent or a D-flip-flop/latch with enable, allows for efficient use of the
FPGA fabric. The VersaTile capability is unique to the Actel ProASIC family of third-generation-
architecture flash FPGAs. VersaTiles are connected with any of the four levels of routing hierarchy.
Flash switches are distributed throughout the device to provide nonvolatile, reconfigurable
interconnect programming. Maximum core utilization is possible for virtually any design.
In addition, extensive on-chip programming circuitry allows for rapid, single-voltage (3.3 V)
programming of RT ProASIC3 devices via an IEEE 1532 JTAG interface.
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FPGA VersaTiles
Dedicated FlashROM
Dedicated SRAM/FIFO memory
Extensive CCCs and PLLs
I/O structure
1-1):
User Nonvolatile
FlashRom
Flash*Freeze
Technology
A dv a n c e v 0. 2
Radiation-Tolerant ProASIC3 Low-Power Space-Flight FPGA
Charge
Pumps
CCC
RAM Block
4,608-Bit Dual-Port SRAM
or FIFO Block
Pro I/Os
VersaTile
RAM Block
4,608-Bit Dual-Port SRAM
or FIFO Block
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