a3pn010 Actel Corporation, a3pn010 Datasheet - Page 16

• Manufacturer Part Number: a3pn010
• Description: Proasic 3 Nano Flash Fpgas
• Manufacturer: Actel Corporation

Radiation-Tolerant ProASIC3 FPGAs
2 -4
I/O Power-Up and Supply Voltage Thresholds for Power-On Reset
Sophisticated power-up management circuitry is designed into every ProASIC
circuits ensure easy transition from the powered-off state to the powered-up state of the device.
The many different supplies can power up in any sequence with minimized current spikes or surges.
In addition, the I/O will be in a known state through the power-up sequence. The basic principle is
shown in
There are five regions to consider during power-up.
RT ProASIC3 I/Os are activated only if ALL of the following three conditions are met:
V
Ramping up: 0.6 V < trip_point_up < 1.2 V
Ramping down: 0.5 V < trip_point_down < 1.1 V
V
Ramping up: 0.6 V < trip_point_up < 1.1 V
Ramping down: 0.5 V < trip_point_down < 1 V
V
specifically built-in hysteresis prevents undesirable power-up oscillations and current surges. Note
the following:
CC
CCI
CC
1. V
2. V
3. Chip is in the operating mode.
•
•
Trip Point:
and V
Trip Point:
Figure 2-3 on page
During programming, I/Os become tristated and weakly pulled up to V
JTAG supply, PLL power supplies, and charge pump V
behavior.
CC
CCI
Figure 2-2 on page 2-5
CCI
and V
> V
ramp-up trip points are about 100 mV higher than ramp-down trip points. This
CC
– 0.75 V (typical)
CCI
are above the minimum specified trip points
2-6).
and
A dv a n c e v 0. 1
Figure 2-3 on page
2-6.
PUMP
supply have no influence on I/O
(Figure 2-2 on page 2-5
CCI
.
®
3 device. These
and