a3pn010 Actel Corporation, a3pn010 Datasheet - Page 2

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a3pn010

Manufacturer Part Number
a3pn010
Description
Proasic 3 Nano Flash Fpgas
Manufacturer
Actel Corporation
Datasheet

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I/Os Per Package
RT ProASIC3 Ordering Information
Radiation-Tolerant ProASIC3
Low-Power Devices
Package
CG/LG484
CG/LG896
CQ256
Notes:
1. When considering migrating your design to a lower- or higher-density device, refer to the packaging section of the
2. Each used differential I/O pair reduces the number of single-ended I/Os available by two.
3. For RT3PE3000L devices, the usage of certain I/O standards is limited as follows:
4. When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not as a regular I/O, the number of single-
Radiation-Tolerant ProASIC3 Low-Power Space-Flight Flash FPGAs
I I
datasheet to ensure you are complying with design and board migration requirements.
– SSTL3(I) and (II): up to 40 I/Os per north or south bank
– LVPECL / GTL+ 3.3 V / GTL 3.3 V: up to 48 I/Os per north or south bank
– SSTL2(I) and (II) / GTL+ 2.5 V / GTL 2.5 V: up to 72 I/Os per north or south bank
ended user I/Os available is reduced by one.
RT3PE3000L
Part Number
RT ProASIC3 Space-Flight FPGAs
RT3PE3000L =
1
RT3PE600L =
_
Single-Ended I/Os
1
TBD
Speed Grade
270
Blank = Standard
600,000 System Gates
3,000,000 System Gates
CG
1 = 15% Faster than Standard
RT3PE600L
2
Package Type
484
Differential I/O Pairs
A d v a n c e v 0 .2
CG = Ceramic Column Grid Array (1.0 mm pitch)
LG = Land Grid Array (1.0 mm pitch)
CQ = Ceramic Quad Flat Pack
Package Lead Count
TBD
135
B
Application (Screening Level)
B = MIL-STD-883 Class B
Single-Ended I/Os
TBD
341
620
RT3PE3000L
2
Differential I/O Pairs
TBD
168
310

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