m52s128324a Elite Semiconductor Memory Technology Inc., m52s128324a Datasheet - Page 15

• Manufacturer Part Number: m52s128324a
• Description: 1m X 32 Bit X 4 Banks Synchronous Dram
• Manufacturer: Elite Semiconductor Memory Technology Inc.

ESMT
COMMANDS
Mode register set command
this command, A0 through A10 and BA0~BA1 are the data input pins. After power on,
the mode register set command must be executed to initialize the device.
other commands.
Activate command
selected by A0 through A10.
Precharge command
When A10 is High, all banks are precharged, regardless of BA1 and BA0. When A10
is Low, only the bank selected by BA1 and BA0 is precharged.
precharging bank during t
Elite Semiconductor Memory Technology Inc.
The M52S128324A has a mode register that defines how the device operates. In
The mode register can be set only when all banks are in idle state.
During 2CLK following this command, the M52S128324A cannot accept any
The M52S128324A has four banks, each with 2,048 rows.
This command activates the bank selected by BA1 and BA0 and a row address
This command corresponds to a conventional DRAM’s RAS falling.
This command begins precharge operation of the bank selected by BA1 and BA0.
After this command, the M52S128324A can’t accept the activate command to the
This command corresponds to a conventional DRAM’s RAS rising.
( CS , RAS , CAS , WE = Low)
( CS , RAS = Low, CAS , WE = High)
( CS , RAS , WE = Low, CAS = High )
RP
(precharge to activate command period).
Publication Date: Mar. 2009
Revision: 1.4
(Precharge select)
M52S128324A
BA0, BA1
(Bank select)
BA0, BA1
(Bank select)
BA0, BA1
(Bank select)
Fig. 2 Row address stroble and
A10
Fig. 3 Precharge command
RAS
CAS
CKE
WE
CLK
CKE
CLK
CKE
RAS
Add
RAS
CAS
CLK
A10
CS
Add
CAS
WE
WE
CS
CS
bank active command
A10
Add
Fig. 1 Mode register set
command
H
H
H
Row
Row
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