m52s128324a Elite Semiconductor Memory Technology Inc., m52s128324a Datasheet - Page 33

• Manufacturer Part Number: m52s128324a
• Description: 1m X 32 Bit X 4 Banks Synchronous Dram
• Manufacturer: Elite Semiconductor Memory Technology Inc.

D Q
C L O C K
A 1 0 / A P
D Q M
ESMT
Page Read & Write Cycle at Same Bank @ Burst Length = 4
W E
Note : 1. To Write data before burst read ends. DQM should be asserted three cycle prior to write command to avoid bus
Elite Semiconductor Memory Technology Inc.
A D D R
C L = 2
C L = 3
C K E
C A S
R A S
B A 1
B A 0
C S
2. Row precharge will interrupt writing. Last data input , t
3. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input
contention.
data after Row precharge cycle will be masked internally.
0
( A - Bank )
Row Active
R a
R a
1
t
2
R C D
3
( A - Bank )
Read
C a
4
5
( A - Bank )
Q a 0
Read
C b
6
Q a1
Q a 0
7
Q a 1
Q b0
8
Q b1
Q b 0
RDL
* N o t e 1
9
before row precharge , will be written.
H I G H
Q b2
Q b1
10
11
( A - Bank )
Write
D c 0
D c 0
C c
t
12
C D L
D c 1
D c 1
13
( A - Bank )
Write
D d 0
D d 0
C d
Publication Date: Mar. 2009
Revision: 1.4
14
D d 1
D d 1
M52S128324A
t
15
R D L
16
* N o t e 2
P r e c h a r g e
( A - B a n k )
* N o t e 3
17
: D o n ' t C a r e
18
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