m52s128324a Elite Semiconductor Memory Technology Inc., m52s128324a Datasheet - Page 30

• Manufacturer Part Number: m52s128324a
• Description: 1m X 32 Bit X 4 Banks Synchronous Dram
• Manufacturer: Elite Semiconductor Memory Technology Inc.

ESMT
Note :
Elite Semiconductor Memory Technology Inc.
1. All input expect CKE & DQM can be don’t care when CS is high at the CLK high going edge.
2. Bank active @ read/write are controlled by BA0~BA1.
3. Enable and disable auto precharge function are controlled by A10/AP in read/write command
4. A10/AP and BA0~BA1 control bank precharge when precharge is asserted.
BA1
A10/AP
A10/AP
0
0
1
1
0
1
0
0
0
0
1
BA0
0
1
0
1
BA1
BA1
X
0
0
1
1
0
0
1
1
0
0
1
1
Active & Read/Write
BA0
BA0
X
0
1
0
1
0
1
0
1
0
1
0
1
Bank C
Bank D
Bank A
Bank B
Disable auto precharge, leave A bank active at end of burst.
Disable auto precharge, leave B bank active at end of burst.
Disable auto precharge, leave C bank active at end of burst.
Disable auto precharge, leave D bank active at end of burst.
Enable auto precharge , precharge bank A at end of burst.
Enable auto precharge , precharge bank B at end of burst.
Enable auto precharge , precharge bank C at end of burst.
Enable auto precharge , precharge bank D at end of burst.
Precharge
All Banks
Bank C
Bank D
Bank A
Bank B
Operating
Publication Date: Mar. 2009
Revision: 1.4
M52S128324A
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