hsp50214a Intersil Corporation, hsp50214a Datasheet - Page 12

• Manufacturer Part Number: hsp50214a
• Description: Programmable Downconverter
• Manufacturer: Intersil Corporation

The integration period counter can be set up to run continu-
ously or to count down and stop. Continuous integration
counter operation lets the counter run, with sampling occurring
every time the counter reaches zero. Because the processor
samples the detector read port asynchronous to the CLKIN,
data can be missed unless the status bit is monitored by the
processor to ensure that a sample is taken for every integration
count down sequence.
Additionally, in the HSP50214A, the ability to align the
start/restart of the input level detector integration period with an
external event is provided. This allows the sync signals, which
are synchronized to external events, to be used to align all of
the gain adjustments or measurements. If Control Word 27, Bit
17 is set to a logic one, the SYNCIN1 signal will cause the input
level detector to start/restart its integration period. If Control
Word 27, Bit 17 is set to a logic zero, control of the start/restart
of the input level detector integration period does not respond to
SYNCIN1.
In the count down and stop mode, the microprocessor read
commands can be synchronized to system events, such as the
start of a burst for a TDMA application. The integration counter
can be started at any time by writing to Control Word 2. At the
end of the integration period (counter = 0000), the upper 23 bits
-12dB
-18dB
-24dB
-30dB
-36dB
-42dB
-48dB
-54dB
-60dB
-66dB
-72dB
-78dB
FIGURE 10. INPUT THRESHOLD DETECTOR BIT WEIGHTING
-6dB
FS
2
2
2
2
2
2
2
2
2
2
2
2
2
2
-10
-11
-12
-13
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
2
2
2
2
2
2
2
2
2
2
2
2
2
2
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
-11
-12
-13
0
2
2
2
2
2
2
2
2
2
2
2
2
2
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
-11
-12
-13
-2
2
2
2
2
2
2
2
2
2
2
2
2
2
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
-11
-12
-13
0
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
-11
-12
-13
HSP50214A
0
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
18
17
16
15
0
-1
-2
-3
-4
14
13
12
11
10
9
8
7
6
5
4
3
2
1
12
of the accumulator are transferred to a holding register for read-
ing by the microprocessor. Note that it is not the restarting of
the counter (by writing to Control Word 2) that latches the cur-
rent value, but the end of the integration count. When the accu-
mulator results are latched, a bit is set in the Status Register to
notify the processor. Reading the most significant byte of the 23
bits clears the status bit. See the Microprocessor Read Section.
Figure 10 illustrates a typical AGC detection process.
Typically, the average input error is read from the Input Level
Detector port for use in AGC Applications. By setting the
threshold to 0, however, the average value of the input signal
can be read directly. The calculation is:
where “level” is the 24-bit value read from the 3 level Detec-
tor Registers and “N” is the number of samples to be inte-
grated. Note that to get the RMS value of a sinusoid, multiply
the average value of the rectified sinusoid by 1.111. For a full
scale input sinusoid, this yields an RMS value of approxi-
mately 3 dBFS.
NOTE: 1.111 scales the rectified sinusoid average (2/ ) to 1/ 2
.
In the HSP50214A, the polarity of the two LSB’s of the inte-
gration period pre-load is selectable. If Control Word 27, Bit
23 is set to a logic one, the two LSB’s of the integration
period preload are set to logic ones. This allows a power of
two to be set for the integration period, for easy normaliza-
tion in the processor. If Control Word 27, Bit 23 is set to a
logic zero, then the two LSB’s of the integration period pre-
load are set to zeros as in the HSP50214.
Carrier Synthesizer/Mixer
The Carrier Synthesizer/Mixer Section of the HSP50214A is
shown in Figure 12. The NCO has a 32-bit phase accumula-
tor, a 10-bit phase offset adder, and a sine/cosine ROM.
A) INPUT SIGNAL
C) THRESHOLD
E) DETECTOR OUTPUT
dBFS
FIGURE 11. SIGNAL PROCESSING WITHIN LEVEL DETECTOR
RMS
=
20
log
1.111 level
B) RECTIFIED SIGNAL
D) ACCUMULATOR INPUTS
F) CLOSED LOOP STEADY STATE
(CONSTANT INPUT)
N 16
(EQ. 2)