hsp50214a Intersil Corporation, hsp50214a Datasheet - Page 38

• Manufacturer Part Number: hsp50214a
• Description: Programmable Downconverter
• Manufacturer: Intersil Corporation

NOTE: In the Status output, BOUT(7:0) are all GND.
Figure 38 shows the interface between a 16-bit microproces-
sor (or other baseband processing engine) and the Buffer
RAM Output Section of the Programmable Down Converter,
configured for data output via the parallel outputs AOUT and
BOUT. In the 16-bit microprocessor interface configuration,
the Buffer RAM pointer is incremented when the Processor
reads address SEL(2:0) = 7 and OEBL = 0.
After reset, the FIFO must be incremented to read the first
sample set. This is because the RAM read and write pointers
cannot point to the same address. Thus, the FIFO pointer
must move to the next address before reading the next set of
data (I, Q, |r|, , and f) samples. 4 PROCCLK cycles are
required after an increment before reading can resume. The
FIFO write pointer is reset to zero (the first data sample) when
Control Word 22 is written to via the 8-bit microprocessor
interface. See the Microprocessor Read Section for more
detail on how to obtain the Buffer RAM output with this tech-
nique. Figure 36 shows the timing diagram required for paral-
lel output operations. In this diagram, only the I, Q and
Frequency data are taken from each sample before incre-
menting to the next sample. Figure 36 assumes that the
pointer has already been incremented into a sample.
NOTE: For the very first sample read, the pointer must be incre-
Figure 39 shows INTRRP going low before the FIFO is read.
The FIFO can be read before the number of samples
reaches the INTRRP pointer. The number of samples in the
FIFO must be monitored by the user via a status read.
LOCATION
AOUT BIT
(7:5)
mented first and 4 PROCCLKs must pass before this
sample can be read.
1-0
4
3
2
TABLE 18. STATUS BIT DEFINITIONS
FIFO depth - When in FIFO mode, these bits
are the current depth of the FIFO.
EMPTY - When in FIFO mode, the FIFO is
empty, and the read pointer cannot be ad-
vanced. Active High.
FULL - When in FIFO mode, the FIFO is full,
and new samples will not be written.
Active High.
READYB - When in FIFO mode, the output buff-
er has reached the programmed threshold. In
the snapshot mode, the programmed number
of samples have been taken. Active Low.
GND
INFORMATION
HSP50214A
38
Suppose the depth of the Buffer RAM Output Section is pro-
grammed for an INTRRP pointer depth of 4. If the output is
at 4 times the baud rate, the processing routine for the
microprocessor may only need to read the buffer when the
Buffer RAM had 4 samples since processing is usually on a
baud by baud basis.
Figure 40 illustrates the conceptual view of the FIFO as a cir-
cular buffer, with the Write address one step ahead of the
Read Address.
Figure 40A deals with clockwise read and write address
incrementing. The FIFO depth is the difference between the
Write and Read pointers, modulo 8. Figure 40B illustrates a
FIFO status of Full, while Figure 40C illustrates a FIFO
empty status condition. Figure 40D illustrates a programmed
FIFO depth of 3 and the INTRRP signal indicating that the
buffer has sufficient data to be read.
Following some simple rules for operating the FIFO will elim-
inate most operational errors:
Rule #1: The Read and Write Pointers cannot point at the
same address (the circuitry will not allow this).
Rule #2: The FIFO is full when the Write Address = Read
Address -1 (no more data will be written until some samples
are read or the FIFO is reset).
FIGURE 38. INTERFACE BETWEEN A 16-BIT MICROPROCES-
FIGURE 39. TIMING DIAGRAM FOR PDC IN FIFO MODE WITH
AOUT(7:0),
BOUT(7:0)
PROCCLK
SEL(0:2)
INTRRP
OEAL,
OEBL
PDC
1 2 3 4
SOR AND PDC IN FIFO BUFFER RAM MODE
OUTPUTS I, Q, AND FREQUENCY SENT TO
AOUT(7:0) AND BOUT(7:0)
8 CLKS
0
I
5 6 7 8
Q
1
AOUT(7:0)
BOUT(7:0)
FR
SEL(2:0)
INTRRP
4
OEAL
OEBL
7
1 2 3 4
> 4 CLKS
I
0
INT
RD
D(15:8)
D(7:0)
A(2:0)
16-BIT
Q
1
P