hsp50214a Intersil Corporation, hsp50214a Datasheet - Page 39

• Manufacturer Part Number: hsp50214a
• Description: Programmable Downconverter
• Manufacturer: Intersil Corporation

Rule #3: The FIFO is empty when the Read Address =
(Write Address -1) (the circuitry will not allow the read
pointer to be incremented).
Rule #4: You cannot write over what you have not read.
Rule #5: RESET places the Write address pointer = 000
and Read address pointer = 111.
Rule #6: The best addressing scheme is to read the FIFO
until it is empty. This avoids erroneous INTRRP assertions
and provides for simple FIFO depth monitoring. The interrupt
is generated when the depth increments past the threshold.
WRITE
D: FIFO READY IS WHEN (WRITE - READ) > DEPTH
FIGURE 40. FIFO REGISTER OPERATION
C: FIFO EMPTY IS WHEN (WRITE - READ) = 1
B: FIFO FULL IS WHEN (WRITE - READ) = 7
A: FIFO DEPTH IS (WRITE - READ)
5
4
5
4
5
4
5
4
6
3
6
3
6
3
6
3
7
2
7
2
7
2
7
2
READY
0
1
0
1
0
1
0
1
READ
WRITE
READ
READ
DEPTH
WRITE
FIFO
WRITE
READ
HSP50214A
39
FIFO Operation via 8-Bit Processor
Interface
The Buffer RAM Output may also be accessed via the 8-bit
microprocessor interface C(7:0). Figure 41 shows the con-
ceptual configuration of the 8-bit processor interface. Con-
trol Word 20, Bit 24 must be set to 0 in order to obtain Buffer
RAM data to this output. The Microprocessor Read Section
describes how to read the data from each sample out of the
C(7:0) interface.
Recall that INTRRP stays low for 8 PROCCLK cycles. The
FIFO can be read before the INTRRP signal goes low; the
number of samples in the FIFO must be monitored by the user.
The timing relationship of the INTRRP to the snapshot data is
shown in Figure 42.
The read pointer of the FIFO is incremented when Control
Word 23 is written to. The data cannot be read from the
next sample until 4 PROCCLKs after the Buffer RAM
pointer has been incremented. Control Word 22 is used to
reset the Read and Write pointers of the Buffer RAM output
to the first sample to 000 and 007 for write and read
respectively.