hsp50214a Intersil Corporation, hsp50214a Datasheet - Page 15

• Manufacturer Part Number: hsp50214a
• Description: Programmable Downconverter
• Manufacturer: Intersil Corporation

CIC Gain Calculations
The gain through the CIC filter increases with increased dec-
imation. The programmable barrel shifter that precedes the
first integrator in the CIC is used to offset this variation. Gain
variations due to decimation should be offset using the 4-bit
CIC Shift Gain word. This allows the input signal level to be
adjusted in 6dB steps to control the CIC output level.
The gain at each stage of the CIC is:
where R is the decimation factor and N is the number of stages.
The input to the CIC from the mixer is 15 bits, and the bit widths
of the accumulators for the five stages in the HSP50214A are
40, 36, 32, 32, and 32, as shown in Figure 16. This limits the
maximum decimation in the CIC to 32 for a full scale input.
If R is 32, the gain through all five integrator stages is 32
(The gain through the last four CIC stages is 2
last 3 it is 2
bits cannot exceed the accumulator size. This means that for a
decimation of 32 and 15 input bits, the first accumulator must
be 15 + 25 = 40 bits.
Thus, the value of the CIC Shift Gain word can be calcu-
lated:
NOTE: The number of input bits is IIN. (If the number of bits into
For 14 bits, Equation 7 becomes:
For 12 bits, Equation 7 becomes:
SG
For 10 bits, Equation 7 becomes:
SG
k
SG
SG = FLOOR 39 - IIN - log
TABLE 3. GAIN ADJUST CONTROL AND CIC DECIMATION
=
=
=
=
=
=
= 15
GAIN VALUE
R
=
= 15
FLOOR 29 log
15
N
FLOOR 27 log
15
FLOOR 25 log
15
the CIC filter is used, the value 40 replaces 39).
,
(dB)
12
18
24
30
36
42
0
6
15
, etc.). The sum of the input bits and the growth
–
–
–
2
2
2
GAIN ADJ(2:0)
R
R
R
5
5
5
for 4
for 6 < R < 52
for 5 < R < 40
for 4
for 4 R 32
for R = 4
for R
000
001
010
011
100
101
110
111
2
(R)
5
=
R
for 4<R<32
for R = 4
R
4
6
5
DECIMATION
MAX. CIC
20
, through the
32
27
24
21
18
16
12
10
(EQ. 8A)
(EQ. 8C)
(EQ. 8B)
5
HSP50214A
(EQ. 7)
(EQ. 6)
= 2
25
.
15
For 8 bits, Equation 7 becomes:
SG
Figure 15 is a plot of Equations 8A through 8D. The 4-bit CIC
Shift Gain word has a range from 0 to 15. The 6-bit CIC Dec-
imation Factor Counter Preload field, (R-1), has a range from
0 to 63, limited by the input resolution as cited above.
Using the Input Gain Adjust Control Signals
The input gain offset control GAINADJ(2:0)) is provided to offset
the signal gain through the part, i.e., to keep the CIC filter output
level constant as the analog front end attenuation is changed.
The gain adjust offset is 6dB per code, so the gain adjust range is
0 to 42dB. For example, if 12dB of attenuation is switched in at
the receiver RF front end, a code of 2 would increase the gain at
the input to the CIC filter up 12dB so that the CIC filter output
would not drop by 12dB. This fixed gain adjust eliminates the
need for the software to continually normalize.
One must exercise care when using this function as it can
cause overflow in the CIC filter. Each gain adjust in the
shifter from the gain adjust control signals is the equivalent
of an extra bit of input. The maximum decimation in the CIC
is reduced accordingly. With a decimation of 32, all 40 bits of
the CIC are needed, so no input offset gain is allowed. As
the decimation is reduced, the allowable offset gain
increases. Table 3 shows the decimation range versus
desired offset gain range. Table 3 assumes that the CIC Shift
Gain has been programmed per Equation 7 or 8A.
The CIC filter decimation counter can be loaded synchronous
with other PDC chips, using the SYNCIN1 signal and the CIC
External Sync Enable bit. The CIC external Sync Enable is set
via Control Word 0, Bit 19.
Halfband Decimating Filters
The Programmable Down Converter has five halfband filter
stages, as shown in Figure 17. Each stage decimates by 2
and filters out half of the available bandwidth. The first half-
band, or HB1, has 7 taps. The remaining halfbands; HB2,
HB3, HB4, and HB5; have 11, 15, 19, and 23 taps respec-
tively. The coefficients for these halfbands are given in Table
4. Figure 18 shows the frequency response of each of the
halfband filters with respect to normalized frequency, F
Frequency normalization is with respect to the input sam-
pling frequency of each filter section. Each stage is activated
by their respective bit location (15-20) in Control Word 7. Any
combination of halfband filters may be used, or all may be
bypassed.
=
=
FLOOR 31 log
15
–
2
R
5
for 4
for 9 < R < 64
R
9
(EQ. 8D)
N
.