hsp50214a Intersil Corporation, hsp50214a Datasheet - Page 31

• Manufacturer Part Number: hsp50214a
• Description: Programmable Downconverter
• Manufacturer: Intersil Corporation

The enable signals associated with the various input selec-
tions to the coordinate converter are:
The discriminator input is 18 bits, and the output is rounded
asymmetrically to 16 bits. The phase into the discriminator
can be multiplied by 2
PSK data modulation. All programmable parameters for the
Frequency Discriminator are set in Control Word 17. Bits 15
and 16 are the phase multiplier which represents the shift
applied to the input phase. For CW, the multiply should equal
2
equal 2
used to enable or disable the discriminator. Bits 11-13 set
the decimation in the programmable FIR filter. Bit 10 sets the
filter symmetry type as either odd or even, bit 9 sets whether
the filter is asymmetric or symmetric, and bits 3-8 set the
number of FIR filter taps. Bits 0-2 set the number of delays in
the frequency discriminator.
Output Section
The Output Section routes the 7 types of processed signals to
output pins in three basic modes. These basic modes are:
Parallel Direct Output, Serial Direct Output, and the Buffer
RAM Output. The Serial and Parallel Direct Output modes
were designed to output data strobes and “real time” continu-
ous streams of data. The Buffer RAM Output mode outputs
data upon receipt of an asynchronous request from an exter-
nal DSP processor or other baseband processing engine. The
use of the interrupt signal from the Programmable Down Con-
verter in conjunction with the request strobes from the control-
ler ensures that data is transferred only when both the
controller and the Programmable Down Converter are ready.
The Buffer RAM output can be operated in a First In First Out
(FIFO) or SNAPSHOT mode with the data output either via the
8-bit processor interface or a 16-bit processor interface.
Parallel Direct Output Port Mode
The Parallel Direct Output Port Mode outputs two 16-bit words,
AOUT and BOUT, of “real time” data. Figure 30 details the par-
allel output circuitry. Selection of the data source for the AOUT
and BOUT parallel outputs is done via Control Word 20, Bits
22-23, and 20-21, respectively. The AOUT port can output I,
Magnitude, or Frequency data. The BOUT port can output Q,
Phase or Magnitude data. The upper bytes of AOUT and
BOUT are always in the parallel direct mode. The 16-bit parallel
direct mode is selected by setting Control Word 20, Bit 25, to
zero.
The DATARDY output is asserted during the first clock cycle
of the new data on the AOUT bus. The rate at which the data
out of the HSP50214 transitions and the rate at which
DATARDY is asserted can be different.
0
, (00). For BPSK, QPSK, and 8PSK, the multiply should
3a
3b
1
The data ready signal to the coordinate converter
block when the resampler is bypassed. This is the
AGC output data ready signal.
The data ready to the coordinate converter block
when the resampler/halfband filters are enabled.
This is the resampler halfband filter block output
data ready signal.
, (01); 2
2
, (10); or 2
0
, 2
1
, 2
2
3
, or 2
, (11); respectively. Bit 14 is
3
(modulo 2 ) to remove
HSP50214A
31
Data Transitions:
The transition rate of the parallel output data is dependent on
which of the three types of data is selected for the AOUT Out-
put channel: I (real symbols), |r| (magnitude), or f (frequency). Q
(quadrature symbols), ø (phase), or |r| (magnitude) are avail-
able on the BOUT output. When selected as an output, the I Q,
|r|, and ø outputs transition at the symbol rate. The f (frequency)
output transitions at the discriminator FIR filter output rate.
†
Controlled via microprocessor interface.
RAM (15:0)
AOUT DIRECT PAR
OUTPUT MODE
DATA SOURCE
BOUT DIRECT PAR
OUTPUT MODE
DATA SOURCE
FIGURE 30. PARALLEL OUTPUT BLOCK DIAGRAM
FREQ
PHAS
MAG
MAG
DATA SOURCE FOR LSB
Q
I
16
16
16
16
16
16
†
†
RAM(15:8)
RAM (7:0)
A(15:8)
A(7:0)
B(15:8)
B(7:0)
†
DATARDY
AOUT(15:8)
AOUT(7:0)
BOUT(15:8)
BOUT(7:0)