ak4665a AKM Semiconductor, Inc., ak4665a Datasheet
ak4665a
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ak4665a Summary of contents
Page 1
... The integrated headphone amplifier features “pop-free” power-on/off, a mute control and delivers 31mW of power into 16Ω load. The AK4665A is housed in a 32pin QFN package, making it suitable for portable applications. ...
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... MS0440-E-01 VREF VCOM VREF VCOM PMVCM PMADC ADC HPF ALC1 PMDAC DATT DEM DAC SMUTE Boost PMHPL or PMHPR or PMLO NVSS Figure 1. Block Diagram - 2 - [AK4665A] DVDD DVSS TVDD MCLK BICK Audio I/F LRCK Controller SDTO SDTI CSN Control CCLK Register CDTI PDN 2006/05 ...
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... AVSS 25 AVDD 26 VCOM 27 VREF 28 PDN 29 CSN 30 CCLK 31 CDTI 32 Comparison Table between AK4569 and AK4665A Function HP-Amp Power Supply HP-Amp Output MIC-Amp MIC-Power ALC for Recording ALC for Playback Loopback SDTO Disable Lineout MCLK Power Supply Package MS0440-E-01 32pin QFN (0.5mm pitch) ...
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... Normally connected to AVSS pin with a 0.1µF ceramic capacitor in parallel with a 4.7µF electrolytic capacitor. VREF pin goes to AVSS when PMVCM bit = ”0”. Power-down Pin 29 PDN I When “L”, the AK4665A is in power-down mode and is held in reset. The AK4665A should always be reset upon power-up. 30 CSN I Control Data Chip Select Pin ...
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... DVDD −0.3 TVDD −0.3 HVDD ∆GND1 - ∆GND2 - IIN - −0.3 VINA −0.3 VIND −30 Ta −65 Tstg Symbol min AVDD 2.6 DVDD 2.6 HVDD 2.6 TVDD 1.6 −0.3 AVDD−DVDD - 5 - [AK4665A] max Units 4.0 V 4.0 V 4.0 V 4.0 V 0.3 V 0.3 V ±10 mA (AVDD+0.3) or 4.0 V (TVDD+0.3) or 4.0 V °C 85 °C 150 typ max Units 3.0 3.6 V 3.0 3 ...
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... HPG bit = “0” =10kΩ 1.35 =16Ω =16Ω =10kΩ [AK4665A] Typ max Units - 20 bit 60 80 kΩ kΩ 1.5 - Vpp 3.0 - Vpp 0.75 - Vpp 0.047 - Vpp − + 2.0 2 kΩ ...
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... Typ max 0.2 - 200 1.35 1.5 1. −30 100 200 −1 0 − +5.5 −6.5 - − +5.5 − [AK4665A] Units - 0 ppm/°C Vpp - kΩ 300 kΩ µA 100 2006/05 ...
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... Note 15. BOOST OFF (BST1-0 bits = “00”) Note 16. LIN→HPL, RIN→HPR, MIN→HPL/HPR. Note 17. These frequency responses scale with fs. If high-level signal is input, the AK4665A clips at low frequency. MS0440-E-01 FILTER CHARACTERISTICS ...
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... High-Level Output Voltage Low-Level Output Voltage (Iout= 100µA) Input Leakage Current MS0440-E-01 DC CHARACTERISTICS Symbol min VIH 70%TVDD VIH 80%TVDD VIL - VIL - VOH TVDD−0.4 VOL - Iin - - 9 - [AK4665A] typ max Units - - 30%TVDD V - 20%TVDD 0.4 V ±10 µA - ...
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... Note 18. Refer to “Serial Data Interface”. Note 19. BICK rising edge must not occur at the same time as LRCK edge. Note 20. The AK4665A can be reset by bringing PDN= “L” to “H” only upon power up. Note 21. This is the count of LRCK “↑” from PMADC bit=”1”. ...
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... LRCK BICK tBCKH LRCK tBLR BICK tLRS SDTO SDTI MS0440-E-01 1/fCLK tCLKL 1/fs tBCK tBCKL Figure 2. Clock Timing tLRB tSDS tSDH Figure 3. Serial Interface Timing - 11 - [AK4665A] VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL tBSD 50%TVDD VIH VIL 2006/05 ...
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... C1 C0 R/W Figure 4. WRITE Command Input Timing Figure 5. WRITE Data Input Timing tPDV Figure 6. Power Down & Reset Timing 1 tPD Figure 7. Power Down & Reset Timing [AK4665A] VIH VIL VIH VIL VIH A4 VIL tCSW VIH VIL tCSH VIH VIL ...
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... PMDAC bit = “1”, PMLO=ALC2 bits = “1” or PMCP=PMHPL=PMHPR bits = “1”). If these clocks are not provided, the AK4665A may draw excess current and will not operate properly because it utilizes these clocks for internal dynamic refresh of registers. If the external clocks are not present, the AK4665A should be placed in power-down mode (PDN pin = “ ...
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... Table 3. Relationship among fs, MCLK frequency and S/N of HP-amp and Lineout Serial Data Interface The AK4665A interfaces with external systems via the BICK, LRCK, SDTO and SDTI pins. Four data formats are available and are selected by setting DIF1-0 bits (Table 4). Mode 0 of SDTI is compatible with existing 16bit DAC and digital filters ...
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... Don’t Care Don’t Care Don’t Care 19 18 Lch Data Figure 11. Mode 3 Timing - 15 - [AK4665A Rch Data ...
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... ASAHI KASEI Digital High Pass Filter The AK4665A has a Digital High Pass Filter (HPF) to cancel DC-offsets in ADC. The cut-off frequency of the HPF is 3.4Hz at fs=44.1kHz. This filter scales with the sampling frequency (fs). Mono-MIC Gain Amplifier (MICIN pin) The AK4665A has a gain amplifier for mono-mic input. The gain of Mic-Amp is selected by MGAIN1-0 bits (see Table 5). The input impedance is 60kΩ ...
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... ASAHI KASEI Input Selector The AK4665A has 2-input selector for ADC. ADC input is selected by INL1, INR1 and INL2 bits. INL1 bit INR1 bit 1 0 The input impedance of stereo line input (AINL1 and AINR1 pins) are 60kΩ(typ). Mono-Record Mode When ADM bit is “1”, ADC Lch data is output on both Lch and Rch of SDTO. ...
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... N [AK4665A] Default Default ZTM=11 3072/fs (69.7ms) Default 2048/fs (64.0ms) 3072/fs (64.0ms) 1536/fs (69.7ms) 1024/fs (64.0ms) 1536/fs (64.0ms) 768/fs (69.7ms) 512/fs (64.0ms) 768/fs (64 ...
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... GAIN STEP 0 1 step 0.375dB 1 2 step 0.750dB 0 3 step 1.125dB 1 4 step 1.500dB Table 13. ALC1 Recovery GAIN Step - 19 - [AK4665A] WTM=11 3072/fs (69.7ms) Default 2048/fs (64.0ms) 3072/fs (64.0ms) 1536/fs (69.7ms) 1024/fs (64.0ms) 1536/fs (64.0ms) 768/fs (69.7ms) 512/fs (64.0ms) 768/fs (64.0ms) Default 2006/05 ...
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... ASAHI KASEI REF7-0 FFH FEH FDH : E2H E1H E0H : 03H 02H 01H 00H Table 14. Reference Level at ALC1 Recovery Operation MS0440-E-01 GAIN(dB) Step +41.25 +40.875 +40.5 : +30.375 0.375dB +30.0 Default +29.625 : −53.25 −53.625 −54.0 MUTE - 20 - [AK4665A] 2006/05 ...
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... E1H +30dB 91H 0dB 00 0.375dB 00 0.375dB 1 Enable Table 15. Example for the ALC1 setting Example: * The value of IVOL should be the same or smaller than REF’ [AK4665A] fs 11.025kHz 12kHz 22.05kHz 24kHz 44.1kHz 48kHz −4.1dBFS −4.1dBFS Enable Enable 8.7ms 8ms 8.7ms 8ms ...
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... If IVOL7-0 bits are written during PMADC bit = “0”, IVOL operation starts with the written values at the end of the ADC initialization cycle after PMADC bit is changed to “1”. IVOL7-0 FFH FEH FDH : 92H 91H 90H : 03H 02H 01H 00H MS0440-E-01 GAIN (dB) Step +41.25 +40.875 +40.5 : +0.375 0.375dB 0.0 −0.375 : −53.25 −53.625 −54 MUTE Table 16. Input Digital Volume - 22 - [AK4665A] Default 2006/05 ...
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... ADC output data is internally passed to DAC when LOOP bit is “1”. The external input data to SDTI pin is ignored. This operation is independent of SDOD bit. MS0440-E-01 Enable E1H(+ 30dB ) E1(+30dB) --> F1(+36dB ) (1) SDOD bit SDTO pin 0 Output Default 1 “L” Table 17. ADC Output ON/OFF LOOP bit DAC Input 0 SDTI pin Default 1 ADC Output Table 18. Digital Loopback - 23 - [AK4665A] Disable E1(+30dB) (2) 2006/05 ...
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... ASAHI KASEI Digital Output Volume (DATT) The AK4665A has a channel-independent digital attenuator (256 levels, 0.5dB step). This digital attenuator is placed before the D/A converter. ATTL/R7-0 bits set the attenuation level (0dB to −127dB or MUTE) for each channel (DATT). At DATTC bit = “1”, ATTL7-0 bits control both Lch and Rch attenuation levels. At DATTC bit = “0”, ATTL7-0 bits control the Lch level and ATTR7-0 bits control the Rch level ...
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... Analog output corresponding to digital input has the group delay (GD). (3) If the soft mute is cancelled within the cycle set by ATS bit, the attenuation is discontinued and returned to the setting value by the same cycle. MS0440-E-01 ATS bit (1) GD (2) Figure 15. Soft Mute Function - 25 - [AK4665A] (3) GD 2006/05 ...
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... ASAHI KASEI De-emphasis Filter (DEM) The AK4665A includes a digital de-emphasis filter (tc = 50/15µs) by IIR filter corresponding to three sampling frequencies (32kHz, 44.1kHz and 48kHz). The de-emphasis filter is enabled by setting DEM1-0 bits (Table 21). DEM1 Bass Boost Function (BOOST) By controlling BST1-0 bits, the bass boost signal can be output from DAC. The setting value is common in Lch and Rch (Table 22) ...
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... When HPG bit = “0” and LING bit = “1”, the gain of LIN/RIN → HPL/HPR paths are −12dB(typ). LIN/RIN/MIN input buffers powered-up when either bits of PMHPL, PMHPR and PMLO bits become “1”. LIN/RIN/MIN pin C MS0440-E-01 AK4665A − Figure 17. External Analog input circuit - 27 - [AK4665A] nd Lineout HP-Amp 2006/05 ...
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... N/A Table 25. ALC2 Limiter Operation Period - 28 - [AK4665A] Default Default LTMP=11 48/fs (1088µs) Default 32/fs (1000µs) 48/fs (1000µs) 24/fs (1088µs) 16/fs (1000µs) 24/fs (1000µs) 12/fs (1088µs) 8/fs (1000µ ...
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... Table 27. ALC2 Recovery Gain Step GAIN(dB) Step +19.5 +19.0 +18.5 +18.0 : +0.5 0.5dB 0.0 −0.5 : −11.0 −11.5 −12 [AK4665A] WTMP=11 24576/fs (557ms) Default 16384/fs (512ms) 24576/fs (512ms) 12288/fs (557ms) 8192/fs (512ms) 12288/fs (512ms) 6144/fs (557ms) 4096/fs (512ms) 6144/fs (512ms) Default Default 2006/05 ...
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... Example: Limiter Cycle = 544 µ fs=44.1kHz Recovery Cycle = 557ms @ fs= 44.1kHz Limiter and Recovery Step = 1 Maximum Gain = +12dB Limiter Detection Level = − 11.5dBV Recovery Transition Time = 139ms @ fs=44.1kHz ALC2 bit = “1” [AK4665A] fs 11.025kHz 12kHz 22.05kHz 24kHz 44.1kHz 48kHz −11.5dBV −11.5dBV 544µ ...
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... EH −4dB DH −6dB −28dB 1H −30dB 0H x MUTE ALC2 LOM bit LOUT pin x Path OFF (L+R)/2 Table 31. Line Output Mode (Lch) LOM bit ROUT pin x Path OFF (L+R)/2 Table 32. Line Output Mode (Rch [AK4665A] Default OPGA LOUT/ ROUT pin Default Default 2006/05 ...
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... Table 34. Headphone output states LINHL/RINHR bit MINHL/MINHR bit DACHL/DACHR bit HPM bit HPL pin x Path OFF (L+R)/2 Table 35. Headphone Output Mode (Lch) HPM bit HPR pin x Path OFF (L+R)/2 Table 36. Headphone Output Mode (Rch [AK4665A] Default Default HPL/HP R pin Default Default 2006/05 ...
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... N [AK4665A] Enable/Disable MOFF0 bit MOFF8 bit MOFF9 bit PUT=11 6146/fs (139ms) Default 4098/fs (128ms) 6146/fs (128ms) 3074/fs (139ms) 2050/fs (128ms) 3074/fs (128ms) ...
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... Table 40. Power up time of Charge Pump Circuit System Reset The AK4665A should be reset once by bringing PDN pin “L” upon power-up. After exiting reset, all blocks (VCOM, ADC, DAC, HPL, HPR, Lineout and charge pump circuit) switch to the power-down state. The contents of the control register are maintained until the reset is done. ADC exits reset and power down state after PMADC bit is changed to “ ...
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... XH, X (3) >0 (5) Don’t care (4) >0 (7) 2081/fs PD(Power-down)Init Cycle Normal Operation (6) (Hi-Z) (8) GD τ = 0.22µF x 30kΩ = 6.6ms (typ) at MGAIN1 bit = “1” τ = 0.22µF x 60kΩ = 13.2ms (typ) at MGAIN1 bit = “0” [AK4665A] 0H, 0 Don’t care PD (Hi-Z) (8) GD 2006/05 ...
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... When PMHPL/R bits = “0”, HPL/R pins are connected to AVSS with internal pull-down resistance (typ 100kΩ). MS0440-E-01 (2) >0 XH, X (3) >0 (4) >0 (5) −HVDD (6) >0 (8) 2081/fs Init Cycle Normal Operation (7) (Hi-Z) (9) GD τ = 1µF x 60kΩ = 60ms (typ) τ = 2.2µF x 17.5kΩ = 38.5ms (typ [AK4665A] 0H, 0 (10) Don’t care 0V PD (Hi-Z) (9) GD 2006/05 ...
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... Clocks should be stopped after PMCP bit is changed to “0”. MS0440-E-01 XH, X XX, XX (3) >0 (4) >0 (5) (6) >0 0V −HVDD Normal Operation MT Normal Operation 00H(MUTE) FFH(0dB) (9) GD (10) 1061/fs (9) (10) (7) (8) τ = 2.2µF x 17.5kΩ = 38.5ms (typ [AK4665A] 0H, 0 00, 00 Don’t care (14 (11 00H(MUTE) (12) (13) 2006/05 ...
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... Digital output corresponding to analog input has the group delay (GD) of 17.5/fs (=397µs@fs=44.1kHz). (7) The transition time for digital volume is set by ATS bit. The initial value is 1061/fs (=24ms@fs=44.1kHz). MS0440-E-01 (1) >150ns (2) >0 (4) Don’t care (3) >0 Normal Operation 00H(MUTE) FFH(0dB) 0FH(0dB) (6) (6) GD (7) 1061/fs (Hi-Z) ( [AK4665A] Don’t care PD 00H(MUTE) 10H (7) (5) (Hi-Z) 2006/05 ...
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... Clocks should be stopped after PMCP bit is changed to “0”. MS0440-E-01 XH, X XX, XX (3) >0 (4) >0 (5) (6) >0 0V −HVDD (7) MT Normal Operation (8) (9) τ = 0.047µF x 200kΩ = 9.4ms (typ) τ = 2.2µF x 17.5kΩ = 38.5ms (typ [AK4665A] 0H, 0 00, 00 Don’t care (13) 0V (Hi-Z) (10 (11) (12) 2006/05 ...
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... PDN= “L”. CSN 0 1 CCLK CDTI C1 C0 R/W MS0440-E- C1-C0: Chip Address (Fixed to “10”) R/W: Read/Write (Fixed to “1”: Write only) A4-A0: Register Address D7-D0: Control Data Figure 26. Control Interface - 40 - [AK4665A 2006/05 ...
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... TEST4 TEST6 TEST5 TEST4 TEST6 TEST5 TEST4 0 0 REFP5 REFP4 HPG LING ALC2 WTMP1 LMTHP PTS1 PTS0 PUT1 PUT0 - 41 - [AK4665A PMHPL PMDAC PMADC PMVCM 0 INR1 INL2 INL1 WTM1 WTM0 0 0 LMAT1 LMAT0 LMTH0 RGAIN0 REF3 REF2 REF1 REF0 ...
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... The register values remain unchanged. Power supply current is 100µA(typ) in this case. For fully shut down (typ. 1µA), PDN pin should be “L”. MS0440-E- PMLO PMHPR [AK4665A PMHPL PMDAC PMADC PMVCM 2006/05 ...
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... ZTM1-0: ALC1 Zero Crossing Timeout Period (Table 11) MGAIN1-0: MIC-Amp Gain (Table 5) MS0440-E- PMMP ADM ZTM1 ZTM0 MGAIN0 [AK4665A INR1 INL2 INL1 WTM1 WTM0 2006/05 ...
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... D4 REF6 REF5 REF4 IVOL6 IVOL5 IVOL4 ATS [AK4665A LMAT1 LMAT0 RGAIN0 LMTH0 REF3 REF2 REF1 REF0 IVOL3 IVOL2 IVOL1 IVOL0 ...
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... MOFF8: Soft transition for changing of DACHL, LINHL, MINHL, DACHR, RINHR, MINHR and HPMTN bits 0: Enable (Default) 1: Disable MS0440-E- SMUTE DATTC MINHR RINHR HPMTN [AK4665A BST1 BST0 DEM1 DEM0 DACHR MINHL LINHL DACHL 2006/05 ...
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... DACR ATTL6 ATTL5 ATTL4 ATTR6 ATTR5 ATTR4 LMUTE [AK4665A MINL RINR LINL DACL ATTL3 ATTL2 ATTL1 ATTL0 ATTR3 ATTR2 ATTR1 ATTR0 ...
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... REFP5 REFP4 HPG LING ALC2 WTMP1 [AK4665A TEST3 TEST2 TEST1 TEST0 TEST3 TEST2 TEST1 TEST0 TEST3 TEST2 TEST1 TEST0 TEST3 TEST2 TEST1 TEST0 REFP3 ...
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... PTS1-0: HP-Amp Mute ON/OFF, Path ON/OFF and ALC2 Recovery Transition Time (Table 39) MS0440-E- LMTHP PTS1 PTS0 PUT1 PUT0 [AK4665A LTMP1 LTMP0 SDOD LOOP FS3 FS2 FS1 FS0 2006/05 ...
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... These capacitors at CP/CN pins and HVSS/NVSS pins require low ESR (Equivalent Series Resistance) over all temperature range. When these capacitors are not bipolar, the positive side should be connected to CP pin and HVSS respectively. - AVSS, DVSS and HVSS of the AK4665A should be distributed separately from the ground of external controllers. - All digital input should not be left floating. ...
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... VCOM and AVSS to eliminate the effects of high frequency noise. A ceramic capacitor should be connected to VCOM pin and located as close as possible to the AK4665A. No load current may be drawn from VREF and VCOM pins. All signals, especially clocks, should be kept away from the VCOM and VREF pins in order to avoid unwanted coupling into the AK4665A ...
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... Note: The exposed pad on the bottom surface of package must be open or connected to ground. Package & Lead frame material Package molding compound: Epoxy Lead frame material: Cu Lead frame surface treatment: Solder (Pb free) plate MS0440-E-01 PACKAGE 0.40 ± 0. C0. [AK4665A] Exposed Pad 32 1 3.5 2006/05 ...
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... AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS0440-E-01 MARKING 4665A XXXXX 1 XXXXX : Date code identifier (5 digits) Revision History Page Contents 1,13,14 MCLK=256fs/384fs/512fs 49 System Design 2Ω series resistor was added at HVDD pin. IMPORTANT NOTICE - 52 - [AK4665A] 256fs/512fs 2006/05 ...