ak4665a AKM Semiconductor, Inc., ak4665a Datasheet - Page 4

• Manufacturer Part Number: ak4665a
• Description: 20-bit Stereo Codec With Mic/hp-amp
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
Note 1. Do not allow digital input pins except analog input pins (MICIN, AINL1, AINR1, LIN, RIN and MIN pins) to
MS0440-E-01
No.
10
11
12
13
14
15
16
17
18
19
20
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23
24
25
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27
28
29
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31
32
1
2
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4
5
6
7
8
9
Pin Name
LRCK
MCLK
BICK
SDTI
SDTO
TVDD
DVSS
DVDD
CP
CN
HVDD
HVSS
NVSS
HPL
HPR
ROUT
LOUT
MIN
RIN
LIN
AINR1
AINL1
MPWR
MICIN
AVSS
AVDD
VCOM
VREF
PDN
CSN
CCLK
CDTI
float.
I/O
O
O
O
O
O
O
O
O
O
O
I
I
-
-
I
-
-
I
I
I
I
I
-
-
I
I
I
-
I
I
I
I
L/R Clock Pin
Master Clock Input Pin
Serial Bit Clock Pin
Audio Data Input Pin
Audio Data Output Pin
Digital I/O Power Supply Pin
Digital Ground Pin
Digital Power Supply Pin
Positive Charge Pump Capacitor Terminal Pin
Negative Charge Pump Capacitor Terminal Pin
Power Supply Pin for Headphone Amplifier and Charge Pump Circuit
Ground Pin for Headphone Amplifier and Charge Pump Circuit
Negative Voltage Output Pin for Headphone Amplifier and Charge Pump Circuit
Lch Headphone Amplifier Output Pin
Rch Headphone Amplifier Output Pin
Rch Analog Output Pin
Lch Analog Output Pin
Mono Analog Input Pin
Rch Analog Input Pin
Lch Analog Input Pin
Rch Analog Input 1 Pin for ADC (LINE Input)
Lch Analog Input 1 Pin for ADC (LINE Input)
MIC Power Supply Pin
MIC Input Pin
Analog Ground Pin
Analog Power Supply Pin
Common Voltage Output Pin, 1.2V (typ, respect to AVSS)
Reference Voltage Output Pin, 2.1V (typ, respect to AVSS)
Reference Voltage Output Pin, 2.1V (typ, respect to AVSS)
Power-down Pin
Control Data Chip Select Pin
Control Clock Input Pin
Control Data Input Pin
Normally connected to AVSS pin with a 0.1µF ceramic capacitor in parallel with a
2.2µF electrolytic capacitor. VCOM pin goes to AVSS when PMVCM bit = ”0”.
Normally connected to AVSS pin with a 0.1µF ceramic capacitor in parallel with a
4.7µF electrolytic capacitor. VREF pin goes to AVSS when PMVCM bit = ”0”.
When “L”, the AK4665A is in power-down mode and is held in reset. The AK4665A
should always be reset upon power-up.
This clock determines which audio channel is currently being output on SDTO pin and
input on SDTI pin.
This clock is used to latch audio data.
SDTO pin goes to DVSS when PDN pin is “L” or PMADC bit is “0”.
HPL pin goes to AVSS when PMHPL bit is “0”.
HPR pin goes to AVSS when PMHPR bit is “0”.
PIN/FUNCTION
- 4 -
Function
[AK4665A]
2006/05