ak4665a AKM Semiconductor, Inc., ak4665a Datasheet - Page 38
ak4665a
Manufacturer Part Number
ak4665a
Description
20-bit Stereo Codec With Mic/hp-amp
Manufacturer
AKM Semiconductor, Inc.
Datasheet
1.AK4665A.pdf
(52 pages)
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ASAHI KASEI
4) DAC → Line Out
(1) PDN pin should be set to “H” at least 150ns after the power is supplied.
(2) DACL and DACR bits should be changed to “1” after PDN pin goes to “H”. Each path is switched-on during the
(3) PMDAC and PMLO bits should be changed to “1” after DACL and DACR pins are changed to “1”.
(4) External clocks (MCLK, BICK and LRCK) are needed to operate DAC. External clocks are also needed for each
(5) When PMLO bit is changed to “1”, pop noise is output from LOUT/ROUT pins.
(6) Digital output corresponding to analog input has the group delay (GD) of 17.5/fs (=397µs@fs=44.1kHz).
(7) The transition time for digital volume is set by ATS bit. The initial value is 1061/fs (=24ms@fs=44.1kHz).
MS0440-E-01
transition time set by FS3-0 and PTS1-0 bits.
path (DACL, LINL, MINL, DACR, RINR and MINR bits) setting.
Power Supply
PDN pin
DACL,
PMVCM bit
Clock Input
PMDAC bit
DAC Internal
SDTI pin
PMLO bit
ATTL/R7-0 bit
LMUTE,
ATTS3-0 bits
LOUT/ROUT pins
DACR bits
State
Figure 24. Power-up/down Sequence of DAC and Line Out
10H(MUTE)
PD(Power-down)
(1) >150ns
Don’t care
(Hi-Z)
00H(MUTE)
(3) >0
(2)
>0
(4)
(5)
(6) GD
- 38 -
Normal Operation
FFH(0dB)
0FH(0dB)
(7) 1061/fs
(6)
(7)
00H(MUTE)
(5)
Don’t care
(Hi-Z)
PD
10H
[AK4665A]
2006/05