wm8400 Wolfson Microelectronics plc, wm8400 Datasheet - Page 105

• Manufacturer Part Number: wm8400
• Description: Wolfson Audioplustm Hi-fi Audio Codec And Power Management Unit For Mobile Multimedia
• Manufacturer: Wolfson Microelectronics plc

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Pre-Production
ALTERNATIVE MCLK INPUT
An alternative MCLK source can be input via the MCLK2/GPIO2 pin. This provides additional
flexibility for systems where the CODEC is required to interface with more than one processor. See
"Clocking and Sample Rates" for more information on selecting MCLK source.
To enable the alternative MCLK input on GPIO2, the following register settings are required:
The above register fields are described in Table 62 and Table 63.
CLOCK OUTPUT
A clock output (OPCLK) derived from SYSCLK may be output via GPIO1 to GPIO6. SYSCLK is
derived from MCLK (either directly, or in conjunction with the FLL), and is used to provide all internal
clocking for the WM8400 (see "Clocking and Sample Rates" section for more information).
A programmable clock divider OPCLKDIV controls the frequency of the OPCLK output. This clock is
enabled by register bit OPCLK_ENA. See “Clocking and Sample Rates” for a definition of this
register field.
To enable clock output via one or more GPIO pins, the following register settings are required:
INVERTED ADCLRC OUTPUT
An inverted ADCLRC signal can be output via the GPIO6/ADCLRCB pin.
To enable the Inverted ADCLRC output, the following register settings are required:
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MCLK_SRC = 1
AIF_TRIS = 0
GPIO2_PU = 0
GPIO2_PD = 0
GPIO2_SEL = 0000
ALRCGPIO1 = 1 (only required if using GPIO1)
MCLK_SRC = 0 (only required if using GPIO2)
AIF_SEL = 0 (only required if using GPIO3, GPIO4 or GPIO5)
ALRCGPIO6 = 0 (only required if using GPIO6)
AIF_TRIS = 0
GPIOn_SEL = 0001 for the selected GPIO clock output pin
GPIOn_PU = 0 for the selected GPIO clock output pin
GPIOn_PD = 0 for the selected GPIO clock output pin
ALRCGPIO6 = 1
AIF_TRIS = 0
GPIO6_PU = 0
GPIO6_PD = 0
PP, April 2009, Rev 3.0
WM8400
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