wm8400 Wolfson Microelectronics plc, wm8400 Datasheet - Page 98

• Manufacturer Part Number: wm8400
• Description: Wolfson Audioplustm Hi-fi Audio Codec And Power Management Unit For Mobile Multimedia
• Manufacturer: Wolfson Microelectronics plc

WM8400
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GPIO POWER DOMAIN
Operation of the GPIO functions or the secondary DAC interface requires an appropriate power
supply to be connected to the I2S2VDD power domain. This supply is referenced to GND. The
operating range for this supply is detailed in the “Recommended Operating Conditions” section.
GPIO CONTROL REGISTERS
Table 62 shows how the dual-function GPIO pins are configured to operate in their different modes.
Note that the order of precedence described earlier applies.
Register field AIF_SEL selects the function of GPIO3, GPIO4 and GPIO5 between Audio Interface 2
and GPIO functions.
Register field ALRCGPIO1 enables the GPIO functionality on GPIO1.
Register field MCLK_SRC enables the GPIO functionality on GPIO2.
Register field ALRCGPIO6 enables the inverted ADCLRC output on GPIO6.
Register bit AIF_TRIS, when set, takes precedence over AIF_SEL, ALRCGPIO1, MCLK_SRC and
ALRCBGPIO6 and tri-states all GPIO pins.
Table 62 GPIO and GPI Pin Function Select
The GPIO pins are also controlled by the register fields described in Table 63. Note the order of
precedence described earlier applies. Accordingly, note that the GPIOn_SEL field is only effective
when GPIOn_PU, GPIOn_PD, AIF_TRIS, AIFSEL, MCLK_SRC, ALRCGPIO1 and ALRCBGPIO6
are set to allow GPIO functionality on that GPIO pin.
The function of the GPIO pins can be selected using the GPIOn_SEL field, where n = 1 to 6,
according to the respective GPIO pin. The available functions are described individually in the
subsequent sections. Internal pull-up and pull-down resistors can be enabled for interfacing with
external signal sources or push-buttons. Pull-down resistors are enabled on GPIO2, GPIO3, GPIO4,
GPIO5 and GPIO6 by default.
Each of the GPIO pins (also including GPI7 and GPI8) may be configured as an input. In this
configuration, the respective GPIO is an input to the CODEC Interrupt function, with selectable
enable, de-bounce and polarity control. The associated interrupt bits (GPIO_STATUS) are latched
once set and can be polled at any time or used to generate CODEC Interrupt events. See “CODEC
Interrupt Event Output” for more details of the CODEC Interrupt event handling.
R8 (08h)
R9 (09h)
R10 (0Ah)
REGISTER
ADDRESS
BIT
15
13
15
14
13
MCLK_SRC
AIF_SEL
ALRCGPIO1
ALRCBGPIO6
AIF_TRIS
LABEL
DEFAULT
0b
0b
0b
0b
0b
MCLK Source Select
0 = MCLK pin
1 = GPIO2/MCLK2 pin
Audio Interface Select
0 = Audio interface 1
1 = Audio interface 2 (GPIO3/BCLK2,
GPIO4/DACLRC2, GPIO5/DACDAT2)
ADCLRC/GPIO1 Pin Function Select
0 = ADCLRC
1 = GPIO1 (ADCLRC connected to
DACLRC internally)
GPIO6/ADCLRCB Pin Function Select
0 = GPIO6
1 = Inverted ADCLRC clock output
Audio Interface and GPIO Tristate
0 = Audio interface and GPIO pins
operate normally
1 = Tristate all audio interface and GPIO
pins
DESCRIPTION
PP, April 2009, Rev 3.0
Pre-Production
98