wm8400 Wolfson Microelectronics plc, wm8400 Datasheet - Page 42

• Manufacturer Part Number: wm8400
• Description: Wolfson Audioplustm Hi-fi Audio Codec And Power Management Unit For Mobile Multimedia
• Manufacturer: Wolfson Microelectronics plc

WM8400
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CLOCKING AND SAMPLE RATES
GPIO6/ADCLRCB
GPIO2/MCLK2
MCLK
ADCLRC
DACLRC
MCLK and MCLK2
MCLK_SRC selects master clock source (MCLK pin or MCLK2/GPIO2 pin)
FLL
FLL_CLK_SRC selects the input reference for FLL oscillator
SYSCLK
All internal clocks are derived from SYSCLK.
SYSCLK can be derived directly from MCLK, MCLK2 or from the FLL output and has a
programmable divide by 2 option (MCLKDIV).
ADC SAMPLE RATE
ADC sample rate is set by ADC_CLKDIV (Master or slave mode).
ADC LRC RATE
ADCLRC in master mode is derived from BCLK and is controlled by ADCLRC_RATE.
DAC SAMPLE RATE
DAC sample rate is set by DAC_CLKDIV (Master or slave mode).
DAC LRC RATE
DACLRC in master mode is derived from BCLK and is controlled by DACLRC_RATE.
BCLK RATE
BCLK rate is set by BCLK_DIV in master mode.
When ADC and DAC operate at different sample rates (in master or slave mode), BCLK
rate should be high enough to support the higher of the ADC and DAC sample rates.
OPCLK RATE
GPIO Clock output frequency is set by OPCLKDIV.
CLASS D SWITCHING RATE
Class D switching can be derived from internal 600kHz clock or from SYSCLK. When
SYSCLK is selected, the frequency is set by DCLKDIV and should be between 700kHz
and 800kHz for best performance.
TOCLK_RATE
A slow clock is used for button/accessory detect de-bounce and for volume update
timeouts (when zero-cross detect is enabled). The frequency of this slow clock is set by
TOCLK_RATE.
Other Sample Rate Controls
DEEMP configures the de-emphasis filter for the chosen sample rate.
MCLK_SRC
The internal clocks for the ADCs, DACs, DSP core functions, digital audio interface and Class D
switching amplifier are all derived from a common internal clock source, SYSCLK. This clock is
enabled by register bit SYSCLK_ENA. Note that many of the analogue audio circuits of the WM8400
can be operated without SYSCLK enabled.
SYSCLK can either be derived directly from MCLK, or may be generated from a Frequency Locked
Loop (FLL) using an external reference. Many commonly-used audio sample rates can be derived
directly from typical MCLK frequencies; the FLL provides additional flexibility to generate a wide
range of SYSCLK frequencies from the available external reference. An alternative MCLK input may
be selected via the GPIO2/MCLK2 pin. All clock configurations must be set up before enabling
playback to avoid glitches.
The ADC and DAC sample rates are independently selectable, relative to SYSCLK, using
ADC_CLKDIV and DAC_CLKDIV. These fields must be set according to the required sampling
frequency and depending on the selected clocking mode (AIF_LRCLKRATE).
In master mode, BCLK is also derived from SYSCLK via a programmable division set by BCLK_DIV.
In the case where the ADCs and DACs are operating at different sample rates, BCLK must be set
according to whichever is the faster rate. The ADCLRC and DACLRC signals do not automatically
match the ADC and DAC sample rates; these must be configured using ADCLRC_RATE and
DACLRC_RATE as described under “Digital Audio Interface Control”.
A clock (OPCLK) derived from SYSCLK can be output on the GPIO pins to provide clocking for other
parts of the system. This clock is enabled by OPCLK_ENA and its frequency is set by OPCLKDIV.
A slow clock (TOCLK) derived from SYSCLK can be used to de-bounce the button/accessory detect
inputs, and to set the timeout period for volume updates when zero-cross detect is used. This clock
is enabled by TOCLK_ENA and its frequency is set by TOCLK_RATE.
The Class D switching amplifier requires a clock; by default, this is derived from SYSCLK via a
programmable divider DCLKDIV. Alternatively, the Class D amplifier clock may be derived from the
WM8400 internal 600kHz clock. (This clock is associated with the DC-DC converters.)
Table 7 to Table 13 show the clocking and sample rate controls for MCLK input, BCLK output (in
master mode), ADCs, DACs, class D outputs and GPIO clock output. The overall clocking scheme
for the WM8400 is illustrated in Figure 17.
Figure 17 CODEC Clocking Scheme
MCLK_INV
FLL_CLK_SRC
f
REF
FLL
f
OUT
SYSCLK_SRC
MCLKDIV[1:0]
00 = MCLK
01 = Reserved
10 = MCLK / 2
11 = Reserved
MCLKDIV[1:0]
f/N
BCLK_DIV[3:0]
0000 = SYSCLK
0001 = SYSCLK / 1.5
0010 = SYSCLK / 2
0011 = SYSCLK / 3
0100 = SYSCLK / 4
0101 = SYSCLK / 5.5
0110 = SYSCLK / 6
0111 = SYSCLK / 8
1000 = SYSCLK / 11
1001 = SYSCLK / 12
1010 = SYSCLK / 16
1011 = SYSCLK / 22
1100 = SYSCLK / 24
1101 = SYSCLK / 32
1110 = SYSCLK / 44
1111 = SYSCLK / 48
DCLKDIV[2:0]
000 = SYSCLK
001 = SYSCLK / 2
010 = SYSCLK / 3
011 = SYSCLK / 4
100 = SYSCLK / 6
101 = SYSCLK / 8
110 = SYSCLK / 12
111 = SYSCLK / 16
SYSCLK_ENA
OPCLKDIV[3:0]
0000 = SYSCLK
0001 = SYSCLK / 2
0010 = SYSCLK / 3
0011 = SYSCLK / 4
0100 = SYSCLK / 5.5
0101 = SYSCLK / 6
0110 = SYSCLK / 8
0111 = SYSCLK / 12
1000 = SYSCLK /16
1001 – 1111 = Reserved
DAC_CLKDIV2:0]
000 = SYSCLK
001 = SYSCLK / 1.5
010 = SYSCLK / 2
011 = SYSCLK / 3
100 = SYSCLK / 4
101 = SYSCLK / 5.5
110 = SYSCLK / 6
111 = Reserved
ADC_CLKDIV[2:0]
000 = SYSCLK
001 = SYSCLK / 1.5
010 = SYSCLK / 2
011 = SYSCLK / 3
100 = SYSCLK / 4
101 = SYSCLK / 5.5
110 = SYSCLK / 6
111 = Reserved
SYSCLK
TOCLK_ENA
f/N
BCLKDIV
[3:0]
DCLKDIV
f/N
Timeout and
De-Bounce
Clock
DACLRC_RATE
[10:0]
f/N
OPCLK_ENA
en
f/N
ADC_CLKDIV
[2:0]
f/N
DAC_CLKDIV
[2:0]
f/N
SYSCLK / N
OPCLKDIV
600kHz
f/N
ADCLRC_RATE
[10:0]
f/2
f/2
DAC_SDMCLK_RATE
21
19
CLASSD_CLK_SEL
OUTPUTS
MASTER
TOCLK_RATE
CLOCK
MODE
f/4
f/4
Button/accessory detect de-bounce,
Volume update timeout
Class D Switching Clock
256fs
256fs
SYSCLK/4
PP, April 2009, Rev 3.0
64fs or
64fs
ADC DSP
GPIO Clock Output
DAC DSP
ADC
DAC
ADCLRCB
ADCLRC
DACLRC, DACLRC2
BCLK, BCLK2
Pre-Production
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