wm8400 Wolfson Microelectronics plc, wm8400 Datasheet - Page 48

• Manufacturer Part Number: wm8400
• Description: Wolfson Audioplustm Hi-fi Audio Codec And Power Management Unit For Mobile Multimedia
• Manufacturer: Wolfson Microelectronics plc

WM8400
w
USB MODE
It is possible to reduce power consumption in the WM8400 by disabling the FLL in some
applications. One such application is when SYSCLK is generated from a 12MHz USB clock source.
Setting the AIF_LRCLKRATE bit as described earlier (see “ADC / DAC Sample Rates”) allows
approximate sample rate close to 44.1kHz to be generated with no additional FLL power
consumption.
In this configuration, SYSCLK must be driven directly from MCLK (or MCLK2) and by disabling the
FLL. This is achieved by setting SYSCLK_SRC=0, FLL_ENA=0 and FLL_OSC_ENA=0.
Table 14 USB Mode Control
FREQUENCY LOCKED LOOP (FLL)
The integrated FLL can be used to generate SYSCLK from a wide variety of different reference
sources and frequencies. The FLL can use either the MCLK or DACLRC input as its reference, which
may be a high frequency (eg. 12.288MHz) or low frequency (eg. 32,768kHz) reference. The FLL is
tolerant of jitter and may be used to generate a stable SYSCLK from a less stable input signal. The
FLL characteristics are summarised in “Electrical Characteristics”.
The analogue and digital portions of the FLL may be enabled independently via FLL_OSC_ENA and
FLL_ENA. When initialising the FLL, the analogue circuit must be enabled first by setting
FLL_OSC_ENA. The digital circuit may then be enabled on the next register write or later. When
changing FLL settings, it is recommended that the digital circuit be disabled via FLL_ENA and then
re-enabled after the other register settings have been updated. When changing the input reference
frequency F
The field FLL_CTRL_RATE controls internal functions within the FLL; it is recommended that only
the default setting be used for this parameter. FLL_TRK_GAIN controls the internal loop gain and
should be set to the recommended value.
The FLL output frequency is directly determined from FLL_FRATIO, FLL_OUTDIV and the real
number represented by FLL_N and FLL_K. The field FLL_N is an integer (LSB = 1); FLL_K is the
fractional portion of the number (MSB = 0.5). The fractional portion is only valid when enabled by the
field FLL_FRAC. It is recommended that FLL_FRAC is enabled at all times.
The FLL frequency is determined according to the following equation:
F
according to the desired output F
Table 15 Choice of FLL_OUTDIV
Note that the output frequencies that do not lie within the ranges quoted above cannot be guaranteed
across the full range of device operating temperatures.
VCO
R11 (0Bh)
2.8125 MHz - 3.125 MHz
5.625 MHz - 6.25 MHz
11.25 MHz - 12.5 MHz
22.5 MHz - 25 MHz
REGISTER
must be in the range 90-100 MHz. The value of FLL_OUTDIV should be selected as follows
ADDRESS
OUTPUT FREQUENCY F
F
F
REF
OUT
VCO
, it is recommended that the FLL be reset by setting FLL_ENA to 0.
= (F
= (F
VCO
REF
10
x N.K x FLL_FRATIO)
/ FLL_OUTDIV)
BIT
AIF_LRCLKRATE
OUT
OUT
.
LABEL
4h (divide by 32)
3h (divide by 16)
2h (divide by 8)
1h (divide by 4)
DEFAULT
0b
FLL_OUTDIV
0 = Normal mode (256 * fs)
1 = USB mode (272 * fs)
LRCLK Rate
DESCRIPTION
PP, April 2009, Rev 3.0
Pre-Production
48