wm8400 Wolfson Microelectronics plc, wm8400 Datasheet - Page 46
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wm8400
Manufacturer Part Number
wm8400
Description
Wolfson Audioplustm Hi-fi Audio Codec And Power Management Unit For Mobile Multimedia
Manufacturer
Wolfson Microelectronics plc
Datasheet
1.WM8400.pdf
(208 pages)
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WM8400
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BCLK CONTROL
In Master Mode, BCLK is derived from SYSCLK via a programmable division set by BCLK_DIV, as
described in Table 10. BCLK_DIV must be set to an appropriate value to ensure that there are
sufficient BCLK cycles to transfer the complete data words from the ADCs and to the DACs.
In Slave Mode, BCLK is generated externally and appears as an input to the CODEC. The host
device must provide sufficient BCLK cycles to transfer complete data words to the ADCs and DACs.
Note that, although the ADC and DAC can run at different sample rates, they will normally share the
same bit clock pin BCLK. In the case where different ADC / DAC sample rates are used, the BCLK
frequency should be set according to the higher of the ADC / DAC bit rates. Note that it is possible
for the ADC and DAC to use independent bit clocks when using the Dual Audio Interface capability -
see “Digital Audio Interface”.
Table 10 BCLK Control
OPCLK CONTROL
A clock output (OPCLK) derived from SYSCLK may be output via GPIO1 to GPIO6. This clock is
enabled by register bit OPCLK_ENA, and its frequency is controlled by OPCLKDIV.
This output of this clock is also dependent upon the GPIO register settings described under “General
Purpose Input/Output”.
Table 11 OPCLK Control
R7 (07h)
R7 (07h)
R3 (03h)
REGISTER
REGISTER
ADDRESS
ADDRESS
4:1
12:9
11
BIT
BIT
BCLK_DIV
[3:0]
OPCLKDIV
[3:0]
OPCLK_ENA
(rw)
LABEL
LABEL
DEFAULT
DEFAULT
0100b
0000b
0b
BCLK Frequency (Master Mode)
0000 = SYSCLK
0001 = SYSCLK / 1.5
0010 = SYSCLK / 2
0011 = SYSCLK / 3
0100 = SYSCLK / 4
0101 = SYSCLK / 5.5
0110 = SYSCLK / 6
0111 = SYSCLK / 8
1000 = SYSCLK / 11
1001 = SYSCLK / 12
1010 = SYSCLK / 16
1011 = SYSCLK / 22
1100 = SYSCLK / 24
1101 = SYSCLK / 32
1110 = SYSCLK / 44
1111 = SYSCL:K / 48
GPIO Output Clock Divider
0000 = SYSCLK
0001 = SYSCLK / 2
0010 = SYSCLK / 3
0011 = SYSCLK / 4
0100 = SYSCLK / 5.5
0101 = SYSCLK / 6
0110 = SYSCLK / 8
0111 = SYSCLK / 12
1000 = SYSCLK / 16
1001 to 1111 = Reserved
GPIO Clock Output Enable
0 = disabled
1 = enabled
DESCRIPTION
DESCRIPTION
PP, April 2009, Rev 3.0
Pre-Production
46
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