ml87v2105 Oki Semiconductor, ml87v2105 Datasheet - Page 10

• Manufacturer Part Number: ml87v2105
• Description: Video Signal Noise Reduction Ic With A Built-in 5.6 Mbit Frame Memory
• Manufacturer: Oki Semiconductor

FUNCTIONAL DESCRIPTION
1 Signal Processing
The ML87V2105 generates memory control signals from the input vertical and horizontal sync signals (IVS and IHS
or SAV and EAV), reads and writes the frame memory data, and performs noise reduction processing on input and
memory data to achieve 3D noise reduction.
1.1 Memory Control
1.1.1 Input Control Mode Settings
The input system internal clock frequency f
Input 16-bit mode: f
Input 8-bit mode/ITU-R BT.656 mode: f
OKI Semiconductor
[0]
0
1
0
1
0
1
VMD
Other than above
From the IVS and IHS or SAV and EAV sync signals, this IC creates memory control signals for video signals
that meet the conditions set forth in Table F1-1. It then writes input data to the frame memory and reduces
frame-recursive noise.
This IC offers a choice of six input control modes, shown below, which can be selected by setting either the
external setting pin mode (IRMON = 0 (SUB:40h–bit [7]) or internal register mode (IRMON = 1).
[1]
0
0
0
0
0
0
Vertical mode
625/50Hz 2:1
525/60Hz 2:1
[0]
0
0
1
1
0
0
HMD
IRMON
0
1
Table F1-1-1 (1) Input/Output Control Mode Setting Allocation
[1]
IICLK
0
0
0
0
1
1
= f
625/50 Hz 2:1
525/60 Hz 2:1
625/50 Hz 2:1
525/60 Hz 2:1
625/50 Hz 2:1
525/60 Hz 2:1
Vertical mode
ICLK
SUB:40h-bit[0]
(External pin)
Valid lines per
Table F1-1-1 (2) Input Control Mode Settings
MODE 0
[0]
field
288
243
Table F1-1 Compatible Input Modes
IICLK
VMD
Number of
valid lines
IICLK
SUB:40h-bit[1]
SUB:40h-bit[1]
= f
288
243
288
243
288
243
Input data sampling
ICLK
is as follows:
frequency (MHz)
[1]
/2
12.272727
14.31818
Test modes (Not settable)
14.75
13.5
13.5
frequency f
Standard clock
12.272727/
14.75/29.5
24.545454
14.75/29.5
14.31818/
28.63636
13.5/27
13.5/27
SUB:40h-bit[2]
[MHz]
(External pin)
MODE 1
[0]
ICLK
pixels per line
*
Standard
HMD
Standard pixels
864
944
858
780
910
SUB:40h-bit[3]
SUB:40h-bit[3]
per line
864
858
944
780
944
910
[1]
horizontal
pixels
PEDL87V2105-02
Valid
720
768
720
640
768
Valid horizontal
ML87V2105
pixels
720
720
768
640
768
768
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