ml87v2105 Oki Semiconductor, ml87v2105 Datasheet - Page 68

• Manufacturer Part Number: ml87v2105
• Description: Video Signal Noise Reduction Ic With A Built-in 5.6 Mbit Frame Memory
• Manufacturer: Oki Semiconductor

2.2.3 Memory control setting 1 (write stop)
OKI Semiconductor
SUB_ADDRESS = 43h(W/R): Memory write stop setting
Register name (Reserved) (Reserved) (Reserved) (Reserved) (Reserved)
SUB_ADDRESS = 44h(W/R): Input system memory control vertical phase adjustment setting
SUB_ADDRESS = 45h(W/R): Input system memory control horizontal phase adjustment setting
Register name (Reserved) (Reserved) (Reserved) (Reserved)
Register name
DATA_BIT
STLM[1:0] Initial value: 0; Setting range: 0 to 1
2.2.4 Memory control setting 2 (phase adjustment)
DATA_BIT
DATA_BIT
STL[2:0] Initial value: 000; Setting range: Refer to Table R2-2-3.
NPVWE[3:0]
Sets input data write stop control.
When data write stops, holds the field data just before the data write stops.
Sets output when input data writing stop is controlled.
When INSINV = 0, sets the number of lines (IHS input count) from the IVS fall position up to the
vertical standard write start position.
When IVSINV = 1, the number of lines is set from the IVS rise position.
Table R2-2-3 (2) Output Mode Settings when Input Data Writing is Stopped
BIT7
BIT7
BIT7
[2]
7
0
0
1
0
0
1
Initial value: 1000; Setting range: 0001 to 1111
Table R2-2-3 (1) Input Data Write Stop Setting
[1]
X
0
1
STL
BIT6
[1]
STLM
X
X
0
1
0
1
BIT6
BIT6
6
[0]
0
1
1
[0]
0
0
0
1
1
1
BIT5
BIT5
BIT5
5
Possible (field B recovery)
Possible (field A recovery)
Possible (arbitrary field recovery)
Stop (field A data hold)
Stop (field B data hold)
Stop (arbitrary field data hold)
Frame output mode (median)
Frame output mode (normal)
Field output mode
BIT4
BIT4
BIT4
NPHWE
Output mode
4
Input data write
BIT3
BIT3
BIT3
3
3
BIT2
BIT2
BIT2
2
2
2
NPVWE
BIT1
BIT1
BIT1
STL
PEDL87V2105-02
1
1
1
ML87V2105
BIT0
BIT0
BIT0
0
0
0
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