ml87v2105 Oki Semiconductor, ml87v2105 Datasheet - Page 58
ml87v2105
Manufacturer Part Number
ml87v2105
Description
Video Signal Noise Reduction Ic With A Built-in 5.6 Mbit Frame Memory
Manufacturer
Oki Semiconductor
Datasheet
1.ML87V2105.pdf
(103 pages)
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PEDL87V2105-02
OKI Semiconductor
ML87V2105
DESCRIPTION OF THE REGISTERS
The IC is equipped with 54 bytes (sub-address 40h to 7Fh) of sub-address registers (8-bit unit) that can access
2
by the I
C-bus interface.
2
Write cycle of the I
C-bus interface returns acknowledge by sub-addresses from 40h to 7Fh.
Regarding the read-only sub-addresses, acknowledge is returned but data write is not performed.
Settings such as mode setting, noise reduction function, memory control function, sync signals generation
become possible by accessing these registers.
All writable registers become readable also.
Note: Blank (reserved) registers must be set to 0.
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