ml87v2105 Oki Semiconductor, ml87v2105 Datasheet - Page 35

• Manufacturer Part Number: ml87v2105
• Description: Video Signal Noise Reduction Ic With A Built-in 5.6 Mbit Frame Memory
• Manufacturer: Oki Semiconductor

1.3.7 Noise Status Detection
OKI Semiconductor
In order to automatically optimize noise reduction setting, this IC has a function for detecting the overall video
sample noise status during the motionless vertical blanking period.
• Detection of noise level (average and maximum values)
The detection starting position is set in DTPSL. When DTPSL = 0, the starting position is immediately after
When NRDTON = 0, the final status data for NRDTON = 1 is preserved. Initially, the average and maximum
The fields for which detection is to be performed are set in NRDTF (SUB:49h-bit[5]). When NRDTF = 0,
Set NRDTON (SUB:49h-bit[1]) = 1 to detect the blanking period noise level for one line (NDTC = 0) of a
vertical blanking period set by NRDTP[3:0](SUB:57h-bit[5:2]) and DTPSL (SUB:57h-bit[7]). Alternatively,
you can set the same register to detect the blanking noise for one line (NDTC = 1) of the maximum noise level
of multiple lines (maximum 16 lines not including valid lines) ending with line NRDTP[3:0]. The blanking
period noise (average and maximum values) detection can be performed frame by frame.
Set PNON (SUB:49h-bit[7]) = 1 to detect the amount of noise in the valid data period.
the end of the valid lines; when DTPSL = 1, the starting position is one line after the end of the valid lines.
noise values are set at 0.
field A vertical blanking period is set; when NRDTF = 1, field B vertical blanking period is set.
By setting YNAMS (SUB:57-bit[0]) and CNAMS (SUB:57h-bit[1]), it is possible to select either an 8-frame
average of the detected noise (YNMAS = 0, CNAMS = 0) or the level of detected noise in a single frame
(YNMAS = 1, CNAMS = 1).
Figure F1-3-7 (1) Vertical Blanking Noise Status Detection timing (NDTC = 0)
Figure F1-3-7 (2) Vertical Blanking Noise Status Detection timing (NDTC = 1)
#Valid data signal
#Valid data signal
#: Internal signal
NRDTP[3:0]
NRDTP[3:0]
NRDTP[3:0]
NRDTP[3:0]
(DTPSL=0)
(DTPSL=1)
#: Internal signal
(DTPSL=0)
(DTPSL=1)
IHS
IHS
0
1
0
2
1
3
2
NDTP[3:0]+1
4
3
NDTP[3:0]+1
5
4
5
14
13
15
14
15
PEDL87V2105-02
ML87V2105
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