ml87v2105 Oki Semiconductor, ml87v2105 Datasheet - Page 11
ml87v2105
Manufacturer Part Number
ml87v2105
Description
Video Signal Noise Reduction Ic With A Built-in 5.6 Mbit Frame Memory
Manufacturer
Oki Semiconductor
Datasheet
1.ML87V2105.pdf
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1.1.2 Input System Field Detection
OKI Semiconductor
The IC input data field is detected from the phase of IVS and IHS to generate the input field pulse (IF) which
controls the internal frame memory.
The field detection pulse can be selected from the IHS (IFLS = 0) or from 0.5H pulse IHALF (IFLS = 1) by
setting the I
In the rear edge of judgment area, since the field judgment uncertainty area contains 10 clocks of IICLK
(internal input system clock), external phase adjustment will be necessary if the phase of IVS lies in this area.
(However, there is no problem if the change of IVS and IHS is in the same phase.)
The device also has the function to automatically generate a field pulse by judging a single field sync signal
input (continuous for more than 8 fields) with the setting of FCON (SUB:42h-bit[7]) = 1. For example, if there
is only field A input, the pulse toggled by IVS is regarded as the field pulse.
0.5H
pulse
0.5H
pulse
IVS
IHS
#IF
IVS
IHS
#IF
2
C-bus setting register IFLS (SUB:42h-bit[3]).
Figure F1-1-2 (1) Input System Field A Detection Timing
Figure F1-1-2 (2) Input System Field B Detection Timing
Field B detection
phase
Field A detection
phase
Field A detection
phase
Field B detection
phase
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