ml87v2105 Oki Semiconductor, ml87v2105 Datasheet - Page 94

• Manufacturer Part Number: ml87v2105
• Description: Video Signal Noise Reduction Ic With A Built-in 5.6 Mbit Frame Memory
• Manufacturer: Oki Semiconductor

2.4.3 Sync Signal Generation Adjustment Settings (for demonstration)
OKI Semiconductor
* The registers in this section are published as settings for generating the necessary sync signals for
monitor display in evaluation boards. Because only standard signals are assumed, the operation of final
products is not guaranteed. Use these settings only when using an evaluation board.
ISYNC Initial value: 0; Setting range: 0 to 1
HSSEL Initial value: 0; Setting range: 0 to 1
SHSDL[7:0] Initial value: 0011_1111; Setting range: 0000_0001 to 1111_1111
Register name
Register name
DATA_BIT
DATA_BIT
OVS and OHS internal sync signal generation settings.
OHS pin output signal settings
Internal sync generator OHS generation start position settings.
SUB_ADDRESS=78h (W/R): Output system memory control mode settings
Table R2-4-3 (2) Internally Generated OVS, OHS Field Settings
Table R2-4-3 (1) Internal Sync Signal Generation Settings
SUB_ADDRESS=79h(W/R): OHS generation start position settings
(Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved)
BIT7
BIT7
7
HSSEL
ISYNC
BIT6
BIT6
0
1
6
0
1
BIT5
BIT5
5
Internally generated output
Horizontal sync signal
OVS and OHS output
Input delay output
Composite sync
BIT4
BIT4
OHS phase
4
SHSDL
BIT3
BIT3
3
BIT2
BIT2
2
HSSEL
BIT1
BIT1
1
PEDL87V2105-02
ISYNC
ML87V2105
BIT0
BIT0
0
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