zl50011 Zarlink Semiconductor, zl50011 Datasheet
zl50011
Related parts for zl50011
zl50011 Summary of contents
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... Copyright 2003-2006, Zarlink Semiconductor Inc. All Rights Reserved. Flexible 512 Channel DX with on-chip ZL50011/QCC ZL50011/GDC 144 Ball LBGA ZL50011QCG1 160 Pin LQFP* ZL50011GDG2 144 Ball LBGA** Trays, Bake & Drypack • Per-stream output channel and output bit delay programming with fractional bit advancement • ...
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... Mbps or 8.192 Mbps on a per-stream basis. The device also provides 16 high impedance control outputs (STOHZ 0-15) to support the use of external high impedance control buffers. The ZL50011 has features that are programmable on a per-stream or per-channel basis including message mode, input bit delay, output bit advancement, constant throughput delay and high impedance output control. ...
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... DPLL Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.11.3 Jitter Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.11.4 Frequency Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.11.5 Locking Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.11.6 Phase Slope 2.11.7 Phase Lock Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.12 Alignment Between Input and Output Frame Pulses 3.0 Oscillator Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.1 External Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.2 External Clock Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.0 Device Reset and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 ZL50011 Table of Contents 3 Zarlink Semiconductor Inc. Data Sheet ...
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... JTAG Support 5.1 Test Access Port (TAP 5.2 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.3 Test Data Register 5.4 BSDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6.0 Register Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.0 Detail Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.0 Connection Memory Bit Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 ZL50011 Table of Contents 4 Zarlink Semiconductor Inc. Data Sheet ...
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... Figure 1 - ZL50011 Functional Block Diagram Figure LQFP (JEDEC MS-026) Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 144 Ball LBGA Pinout Diagram Figure 4 - Input Timing when (CKIN2 to CKIN0 bits = 010) in the Control Register . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 5 - Input Timing when (CKIN2 to CKIN0 bits = 001) in the Control Register . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 6 - Input Timing when (CKIN2 to CKIN0 bits = 000) in the Control Register ...
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... Figure 46 - Output Driver Enable (ODE Figure 47 - Motorola Non-Multiplexed Bus Timing Figure 48 - JTAG Test Port Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Figure 49 - Reset Pin Timing Diagram ZL50011 List of Figures 6 Zarlink Semiconductor Inc. Data Sheet ...
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... Table 31 - Stream Output Offset Register (SOOR8 to SOOR15 Table 32 - Address Map for Memory Locations (512x512 DX, MSB of address = 1 Table 33 - Connection Memory Bit Assignment when the CMM bit = Table 34 - Connection Memory Bits Assignment when the CMM bit = ZL50011 List of Tables 7 Zarlink Semiconductor Inc. ...
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... Input Jitter Tolerance with Frame Boundary Determinator“ 47 Table 16 - “Control Register (CR) Bits“ - bits “FBDMODE“ and “FBDEN“ ZL50011 • Clarified initialization input clock requirement in DPLL Bypass mode. • Added a new section to describe the improved input jitter tolerance with the frame boundary determinator. • ...
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... VSS 155 156 VDD 157 RESET 158 TDo 159 NC 160 NC Figure LQFP (JEDEC MS-026) Pinout Diagram ZL50011 160 Pin LQFP 0.5 mm pin pitch JEDEC MS-026 (Top View) 9 Zarlink Semiconductor Inc. Data Sheet VDD ...
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... STo2 D STo3 E STo5 F STo6 G STOHZ 6 H STo9 J STo11 K STOHZ 9 L STOHZ 10 M STo14 Figure 144 Ball LBGA Pinout Diagram ZL50011 FPo2 FPo0 ICONN IC1 IC0 XTALi XTALo TM1 1 CKo1 FPo1 CKo0 IC3 IC2 CLK VDD_ ...
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... B12 4 A12 5 B11 6 A11 7 B10 8 A10 ZL50011 Name V Power Supply for the device: +3 (GND) Ground. ss TMS Test Mode Select (3.3 V Tolerant Input with internal pull-up): JTAG signal that controls the state transitions of the TAP controller. This pin is pulled high by an internal pull-up resistor when it is not driven ...
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... A6, A5, B6, B5 ZL50011 Name SG1 APLL Test Control (3.3 V Input with internal pull-down): For normal operation, this input MUST be low. TM1 APLL Test Pin 1: For normal operation, this input MUST be low. TM2 APLL Test Pin 2: For normal operation, this input MUST be low ...
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... E2, E1, F1 H3, H1, H2 L2, L3, M1, K3 ZL50011 Name CKo0 ST-BUS Clock Output Tolerant Three-state Output): A 4.094 MHz or 8.192 MHz clock output. The clock falling edge defines the output frame boundary. The polarity of this signal can be changed using the Internal Mode Selection register. ...
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... D10, E10, F11 150 - 152 F12, E12, E11 153, 154 D12, C12 ZL50011 Name Serial Output Streams High Impedance Control Tolerant Three-state Outputs): These pins are used to enable (or disable) external three-state buffers. When an output channel is in the high impedance state, the STOHZ drives high for the duration of the corresponding output channel ...
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... C5 42 82, 119 - 122, 159, 160 ZL50011 Name RESET Device Reset (5 V Tolerant Input): This input (active LOW) puts the device in its reset state that disables the STo0 - 15 drivers and drives the STOHZ outputs to high. It also clears the device registers and internal counters. To ensure proper reset action, the reset pin must be low for longer than 1 ms ...
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... Mbps respectively. The frequency of CKi must be twice the highest data rate. For example, if users present the ZL50011 with 2.048 Mbps and 8.192 Mbps input data, the device should be programmed to accept the input clock of 16.384 MHz and the frame pulse which stays low for 61 ns. ...
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... FPi FPINP = 0 FPi FPINP = 1 CKi (16.384 MHz) CKINP = 0 CKi (16.384 MHz) CKINP = 1 Figure 6 - Input Timing when (CKIN2 to CKIN0 bits = 000) in the Control Register ZL50011 CKi 61 ns 16.384 MHz 122 ns 8.192 MHz 244 ns 4.096 MHz Reserved Input Frame Boundary Input Frame Boundary ...
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... Improved Input Jitter Tolerance with Frame Boundary Determinator The ZL50011 has a Frame Boundary Determinator (FBD) allowing substantial increase of the CKi input clock jitter tolerance. The FBD circuit is enabled by setting the Control Register bits FBDEN and FBDMODE to HIGH. By default the FBD is disabled. Both the FBDEN and FBDMODE bits should be set HIGH during normal operation. The device can have input clock jitter tolerance (on CKi and FPi) when the FBD is fully enabled ...
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... CKFP0 0 1 Table 2 - FPo0 and CKo0 Output Programming CKFP1 0 1 Table 3 - FPo1 and CKo1 Output Programming CKFP2 0 1 Table 4 - FPo2 and CKo2 Output Programming ZL50011 FPo0 CKo0 Low Cycle 244 ns 4.096 MHz 122 ns 8.192 MHz FPo1 CKo1 61 ns 16.384 MHz 122 ns 8 ...
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... MHz) CK1P = 1 Figure 10 - FPo1 and CKo1 Output Timing when the CKFP1 Bit = 0 FPo1 FP1P = 0 FPo1 FP1P =1 CKo1 (8.192 MHz) CK1P = 0 CKo1 (8.192 MHz) CK1P = 1 Figure 11 - FPo1 and CKo1 Output Timing when the CKFP1 Bit = 1 ZL50011 20 Zarlink Semiconductor Inc. Data Sheet ...
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... CKo2 (32.768 MHz) CK2P = 1 Figure 12 - FPo2 and CKo2 Output Timing when the CKFP2 Bit = 0 FPo2 FP2P = 0 FPo2 FP2P = 1 CKo2 (16.384MHz) CK2P = 0 CKo2 (16.384 MHz) CK2P = 1 Figure 13 - FPo2 and CKo2 Output Timing when the CKFP2 Bit = 1 ZL50011 21 Zarlink Semiconductor Inc. Data Sheet ...
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... Mbps) STo (4.096 Mbps) Channel 0 STo (8.192 Mbps) Output Frame Boundary Figure 14 - ST-BUS Output Timing for Various Output Data Rates ZL50011 Channel Channel Channel ...
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... By default, all input streams have zero bit delay such that Bit 7 is the first bit that appears after the input frame boundary, see Figure 16. The input delay is enabled by Bit the Stream Input Delay Registers (SIDR). The input bit delay can vary from bits. ZL50011 ...
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... Channel Delay = 2 Note Note: Last Channel = 31, 63, 127 for 2.048 Mbps, 4.096 Mbps and 8.192 Mbps mode respectively Output Frame Boundary Figure 17 - Output Channel Delay Timing Diagram ZL50011 Ch0 Bit Delay = 1 Ch0 1 ...
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... Fractional Bit Advancement = 1/4 bit SToY Bit 1 Fractional Bit Adv. = 1/4 bit Note Note: Last Channel = 31, 63, 127 for 2.048 Mbps, 4.096 Mbps and 8.192 Mbps mode respectively Figure 19 - Fractional Output Bit Advancement Timing Diagram ZL50011 Ch0 ...
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... Adv.) Note Output Frame Boundary Note: Last Channel = 31, 63, 127 for 2.048 Mbps, 4.096 Mbps and 8.192 Mbps mode respectively Figure 20 - Example: External High Impedance Control Timing ZL50011 HiZ Ch2 Ch3 Ch1 STOHZ Advancement (Programmable in 4 steps of 15 1/4 bit) 26 Zarlink Semiconductor Inc ...
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... Table 6 - Variable Range for Output Streams Input Channel Delay OFF Input Channel Delay ON Output Channel Delay OFF Output Channel Delay OFF frames - α + (n- frames + (n-m) ZL50011 Input Channel Possible Input channel delay (α) Number ( 127 Output Channel ...
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... Frame N-2 Data (β Serial Output Data Frame N-3 Data (β > 1) Figure 23 - Data Throughput Delay when Input Channel Delay is Disabled and Output Channel Delay is Enabled for Input Ch0 Switch to Output Ch0 ZL50011 Frame N+1 Frame N+2 Frame N+3 Frame N+1Data Frame N+2 Data Frame N+3 Data 2 Frames + 0 ...
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... This feature allows fast initialization of the entire connection memory after power up. When block programming mode is enabled, the content of Bit the Internal Mode Selection (IMS) Register will be loaded into Bit all the 512 connection memory locations. The other bit positions of the connection memory will be loaded with zeros. ZL50011 Frame N+1 Frame N+2 Frame N+3 ...
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... Bit Error Rate (BER) Test The ZL50011 has one on-chip BER transmitter and one BER receiver. The transmitter can transmit onto a single STo output stream only. The transmitter provides a BER sequence (2 from any channel in the frame and lasts from one channel up to one frame time (125 µs). The transmitter output ...
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... No bit replacement occurs in Quadrant 0 Table 10 - Quadrant Frame 0 LSB Replacement STIN#QEN1 1 Replace LSB of every channel in Quadrant 1 with "1" bit replacement occurs in Quadrant 1 Table 11 - Quadrant Frame 1 LSB Replacement ZL50011 Quadrant 1 Quadrant ...
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... In Bypass mode, the DPLL is completely bypassed. The Analog Phase-Locked Loop (APLL) synchronizes to the ST-BUS input clock CKi to generate the internal clock MCKTDM. Bypass mode is used when the system’s ST-BUS timing is supplied by another device, e.g. another ZL50011 in Master mode. ZL50011 Action ...
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... If a ZL50011 operated exclusively in Freerun mode, then its ST-BUS output clock and frame pulse must be used as the ST-BUS input clock and frame pulse to all TDM devices in the system, including the device itself. ...
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... MHz oscillator is not required, but the XTALi pin should still get a valid clock signal so that the device can be initialized. The easiest way is to tie the CKi clock to the XTALi pin. The XTALo pin must be left unconnected. Bypass mode is used when another device, such as another ZL50011 in Master mode, is providing system timing. 2.10 DPLL Functional Description Figure 25 shows the functional block diagram of the DPLL ...
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... If the programmed frequency is 1.544 MHz or 2.048 MHz, the "64 periods in specified range" check will be performed. The time taken for 64 consecutive cycles must be between 62 and 66 periods of the programmed frequency. ZL50011 Figure 26 - Skew Control Circuit Diagram 35 Zarlink Semiconductor Inc. Data Sheet ...
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... MCKTDM clock in Figure 25 on page 34 and Figure 27 on page 36. MCKTDM provides timing for the TDM switching function, and timing for the ST-BUS outputs. When the DPLL is in Freerun mode, the frequency offset is ignored and the DCO is free running at its preset center frequency. ZL50011 Phase Loop Slope ...
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... Since intrinsic jitter is always present, jitter attenuation will appear to be lower for small input jitter signals than for large ones. Consequently, accurate jitter transfer function measurements are usually made with large input jitter signals (e.g., 75% of the specified maximum jitter tolerance). ZL50011 37 Zarlink Semiconductor Inc. ...
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... APLL generates the DPLL master clock from the oscillator. Thus the DPLL free run accuracy is affected by the oscillator accuracy. The DPLL free run accuracy is -0.03 ppm plus the accuracy of the oscillator. Figure 28 - DPLL Jitter Transfer Function Diagram - Wide Range of Frequencies ZL50011 38 Zarlink Semiconductor Inc. ...
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... Lock time is very difficult to determine because it is affected by many factors which include: i) initial input to output phase difference ii) initial input to output frequency difference iii) PLL loop filter iv) PLL limiter ZL50011 39 Zarlink Semiconductor Inc. Data Sheet ...
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... The easiest way is to tie the CKi clock to the XTALi pin. The XTALo pin must be left unconnected. 3.1 External Crystal Oscillator A complete external crystal oscillator circuit made crystal, resistor and capacitors is shown in Figure 30. ZL50011 1uH inductor: may improve stability and is optional ZL50011 XTALi 20 MHz 1MΩ 3-50 pF XTALo 100Ω ...
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... V 2. pF) Duty Cycle: 40% to 60% The output clock should be connected directly (not AC coupled) to the XTALi input of the device, and the XTALo output should be left open as shown in Figure 31. ZL50011 Figure 31 - External Clock Oscillator Circuit ZL50011 Ω +3.3 V XTALi +3 MHz OUT GND ...
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... Test Access Port (TAP) Controller. 5.1 Test Access Port (TAP) The Test Access Port (TAP) accesses the ZL50011 test functions. It consists of 3 input pins and 1 output pin as follows: • Test Clock Input (TCK) - TCK provides the clock for the test logic. The TCK does not interfere with any on-chip clock and thus remains independent in the functional mode ...
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... Instruction Register The ZL50011 uses the public instructions defined in the IEEE 1149.1 standard. The JTAG Interface contains a four-bit instruction register. Instructions are serially loaded into the instruction register from the TDI when the TAP Controller is in its shifted-IR state. These instructions are subsequently decoded to achieve two basic functions: to select the test data register that may operate while the instruction is current and to define the serial test data register path that is used to shift data between TDI and TDO during data register scanning ...
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... H 111 H 112 H 113 H 114 H 115 H 116 H Table 15 - Address Map for Device Specific Registers ZL50011 CPU Register R/W Control Register, CR R/W Internal Mode Selection, IMS R/W BER Start Receive Register, BSRR R/W BER Length Register, BLR BER Count Register, BCR R/W DPLL Operation Mode, DOM R/W DPLL Output Adjustment, DPOA ...
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... ZL50011 External CPU Address Access A11 - A0 117 R/W Stream11 Input Delay Register, SIDR11 H 118 R/W Stream12 Input Control Register, SICR12 H 119 R/W Stream12 Input Delay Register, SIDR12 H 11A R/W Stream13 Input Control Register, SICR13 H 11B R/W Stream13 Input Delay Register, SIDR13 H 11C R/W Stream14 Input Control Register, SICR14 ...
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... ZL50011 External CPU Address Access A11 - A0 217 R/W Stream11 Output Delay Register, SOOR11 H 218 R/W Stream12 Output Control Register, SOCR12 H 219 R/W Stream12 Output Delay Register, SOOR12 H 21A R/W Stream13 Output Control Register, SOCR13 H 21B R/W Stream13 Output Delay Register, SOOR13 H 21C R/W Stream14 Output Control Register, SOCR14 ...
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... CKFP0 Output ST Bus clock CKo0 and frame pulse FPo0 Selection. When this bit is low, CKo0 is 4.096 MHz clock and FPo0 is 244 ns wide frame pulse When this bit is high, CKo0 is 8.192 MHz clock and FPo0 is 122 ns wide frame pulse ZL50011 ...
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... Output Stand By Bit: This bit enables the STo0 - 15 and the STOHZ 0 -15 serial outputs. following table describes the HiZ control of the serial data outputs MS2-0 Memory Select Bit. These bits are used to select connection memory or data memory: Table 16 - Control Register (CR) Bits (continued) ZL50011 CKFP ...
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... After the MBPE bit in the control register is set to high and the MBPS bit is set to high, the contents of the bits BPD0 to BPD2 are loaded into Bit 0 to Bit 2 of the connection memory. Bit 3 to Bit 11 of the connection memory are zeroed. Table 17 - Internal Mode Selection (IMS) Register Bits ZL50011 ...
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... BER Receive Stream Address Bits: The binary value of these bits refers to the input stream which receives the BER data BRCA6 - 0 BER Receive Channel Address Bits: The binary value of these bits refers to the input channel in which the BER data starts to be compared. Table 18 - BER Start Receiving Register (BSRR) Bits ZL50011 CK2P ...
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... Bit Name BC15 - 0 BER Count Bits: The binary value of these bits refers to the bit error counts. When it reaches its maximum value of Hex FFFF, the value will not be changed any more. Table 20 - BER Count Register (BCR) Bits ZL50011 ...
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... Freerun Control Bit: When this bit is low and bit 14 of the Control Register is low, the DPLL is in Master mode. When this bit is high and bit 14 of the Control Register is low, the DPLL is in Freerun mode. This bit has no effect when bit 14 of the Control Register is high. Table 21 - DPLL Operation Mode (DOM) Register Bits ZL50011 ...
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... DPLL LIMIT Bit (Read only bit): This bit indicates that the Phase Slope Limiter is limiting the phase difference between the input reference and the feedback reference Unused Reserved Bits (Read only bits): The content from reading these bits is undefined. Table 23 - DPLL House Keeping (DHKR) Register Bits ZL50011 ...
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... When this bit is high, the LSB of every channel in this quadrant frame is replaced by "1". This quadrant frame is defined as Ch0 to 7, Ch0 to 15 and Ch0 to 31 for 2.048 Mbps, the 4.096 Mbps and 8.192 Mbps mode respectively. Table 24 - Stream Input Control Register (SICR0 to SICR7) ZL50011 , 102 , 104 ...
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... Bit Name Input Data Sampling Point Selection Bits STIN#SMP1 - STIN#DR2 - 0 Input Data Rate Selection Bits: Note: # denotes input stream from Table 24 - Stream Input Control Register (SICR0 to SICR7) (continued) ZL50011 , 102 , 104 , 106 , 108 ...
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... When this bit is high, the LSB of every channel in this quadrant frame is replaced by "1". This quadrant frame is defined as Ch0 to 7, Ch0 to 15 and Ch0 to 31 for 2.048 Mbps, the 4.096 Mbps and 8.192 Mbps mode respectively. Table 25 - Stream Input Control Register (SICR8 to SICR15) ZL50011 , 112 , 114 ...
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... Bit Name Input Data Sampling Point Selection Bits STIN#SMP1 - STIN#DR2 - 0 Input Data Rate Selection Bits: Note: # denotes input stream from Table 25 - Stream Input Control Register (SICR8 to SICR15) (continued) ZL50011 , 112 , 114 , 116 , 118 ...
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... Input Stream# Bit Delay Bits: The binary value of these bits refers to the number of bits that the input stream will be delayed. This maximum value is 7. Zero means no delay. Note: # denotes input stream from Table 26 - Stream Input Delay Register (SIDR0 to SIDR7) ZL50011 , 103 , 105 ...
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... Input Stream# Bit Delay Bits: The binary value of these bits refers to the number of bits that the input stream will be delayed. This maximum value is 7. Zero means no delay. Note: # denotes input stream from Table 27 - Stream Input Delay Register (SIDR8 to SIDR15) ZL50011 , 113 , 115 ...
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... STOHZ Advancement Control. When this bit is low, the advancement unit is 15.2 ns. When this bit is high, the advancement unit is 1/4 bit. STOHZ Additional Advancement Bits STOHZ# STO#DR2 - 0 Output Data Rate Selection Bits: Note: # denotes input stream from Table 28 - Stream Output Control Register (SOCR0 to SOCR7) ZL50011 , 202 , 204 , 206 , 208 H ...
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... STOHZ Advancement Control. When this bit is low, the advancement unit is 15.2 ns. When this bit is high, the advancement unit is 1/4 bit. STOHZ Additional Advancement Bits STOHZ# STO#DR2 - 0 Output Data Rate Selection Bits: Note: # denotes input stream from Table 29 - Stream Output Control Register (SOCR8 to SOCR15) ZL50011 , 212 , 214 , 216 , 218 H ...
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... The binary value of these bits refers to the number of bits that the output stream delayed. The maximum value is 7. Zero means no delay STO#FA1-0 Output Stream# Fractional Advancement Bits Note: # denotes input stream from Table 30 - Stream Output Offset Register (SOOR0 to SOOR7) ZL50011 , 203 , 205 , 207 ...
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... The binary value of these bits refers to the number of bits that the output stream delayed. The maximum value is 7. Zero means no delay STO#FA1-0 Output Stream# Fractional Advancement Bits Note: # denotes input stream from Table 31 - Stream Output Offset Register (SOOR8 to SOOR15) ZL50011 , 213 , 215 , 217 ...
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... Channels are used when serial stream is at 2.048 Mbps. 3. Channels are used when serial stream is at 4.096 Mbps. 4. Channels 0 to 127 are used when serial stream is at 8.192 Mbps. Table 32 - Address Map for Memory Locations (512x512 DX, MSB of address = 1) ZL50011 A7 Stream # A6 ...
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... Per-Channel Control Bits: These two bits control outputs. 0 CMM=1 Connection Memory Mode = 1. If this bit is set high, the connection memory is in the per-channel control mode which is per-channel tristate, per-channel message mode or per-channel BER mode. Table 34 - Connection Memory Bits Assignment when the CMM bit = 1 ZL50011 SSA0 ...
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... Characteristics are over recommended operating conditions unless otherwise stated. ° ‡ Typical figures are 3.3 V and are for design aid only: not guaranteed and not subject to production testing. DD Note 1: Maximum leakage on pins (output or I/O pins in high impedance state) is over an applied voltage ( ZL50011 Sym I_3V V ...
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... CKi Input Clock Rise/Fall Time † Characteristics are over recommended operating conditions unless otherwise stated. ° ‡ Typical figures are 3.3 V and are for design aid only: not guaranteed and not subject to production testing. DD ZL50011 † - Timing Parameter Measurement Voltage Levels Sym. Level V 0.5V ...
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... Typical figures are at 25° 3.3 V and are for design aid only: not guaranteed and not subject to production testing. DD Input Frame Boundary N FPi CKi Figure 33 - Frame Boundary Timing with Input Clock (Cycle-to-Cycle) Variation ZL50011 t FPIW t FPH t CKIL † - Frame Boundary Timing with Input Clock Cycle-to-cycle Sym ...
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... V and are for design aid only: not guaranteed and not subject to production testing. DD Input Frame Boundary N FPi CKi Figure 34 - Frame Boundary Timing with Input Frame Pulse (Cycle-to-Cycle) Variation ZL50011 † - Frame Boundary Timing with Input Frame Pulse Sym. Min ...
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... Typical figures are at 25° 3.3 V and are for design aid only: not guaranteed and not subject to production testing. DD XTALi Figure 35 - XTALi Input Timing Diagram when Clock Oscillator is Connected ZL50011 † - XTALi Input Timing when Clock Oscillator is connected Sym. Min. ...
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... Figure 36 - Reference Input Timing Diagram when the Input Frequency = 8 kHz REF (2.048MHz) Figure 37 - Reference Input Timing Diagram when the Input Frequency = 2.048 MHz REF (1.544MHz) Figure 38 - Reference Input Timing Diagram when the Input Frequency = 1.544 Hz ZL50011 Sym. Min. t R8KP 122 t R8KH 0.09 t R8KL 0 ...
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... Input Frame Boundary FPo2 CKo2 (32.768MHz) FPo2 or FPo1 CKo2 or FPo1 (16.384MHz) FPo1 or FPo0 CKo1 or CKo0 (8.192MHz) FPo0 CKo0 (4.096MHz) Figure 39 - Input and Output Frame Boundary Offset ZL50011 Sym. Min. Typ. Max. t FBOS - FBOS FBOS Output Frame Boundary 72 Zarlink Semiconductor Inc. ...
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... Typical figures are 3.3 V and are for design aid only: not guaranteed and not subject to production testing. DD FPo0 CKo0 Output Frame Boundary Figure 40 - FPo0 and CKo0 Timing Diagram ZL50011 † - FPo0 and CKo0 Timing when CKFP0 = 0 Sym. Min. Typ. t 220 FPW0 ...
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... Typical figures are 3.3 V and are for design aid only: not guaranteed and not subject to production testing. DD FPo1 CKo1 Output Frame Boundary Figure 41 - FPo1 and CKo1 Timing Diagram ZL50011 † - FPo1 and CKo1 Timing when CKFP1 = 0 Sym. Min FPW1 ...
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... Typical figures are 3.3 V and are for design aid only: not guaranteed and not subject to production testing. DD FPo2 CKo2 Output Frame Boundary Figure 42 - FPo2 and CKo2 Timing Diagram ZL50011 † - FPo2 and CKo2 Timing when CKFP2 = 0 Sym. Min FPW2 ...
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... STi0 - 15 Bit0 2.048 Mbps Ch31 STi0 - 15 Bit0 4.096 Mbps Ch63 STi0 - 15 Bit1 Bit0 Ch127 Ch127 8.192 Mbps Input Frame Boundary Figure 43 - ST-BUS Inputs (STi0 - 15) Timing Diagram ZL50011 † - ST-BUS Input Timing ‡ Sym. Min. Typ. Max SIS2 3 t SIS4 3 t SIS8 ...
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... CKo0 (4.096MHz) STo0 - 15 Bit7 Ch31 2.048 Mbps STo0 - 15 Bit7 4.096 Mbps Ch63 STo0 - 15 Bit0 Ch127 8.192 Mbps Output Frame Boundary Figure 44 - ST-BUS Outputs (STo0 - 15) Timing Diagram ZL50011 † - ST-BUS Output Timing ‡ Sym. Min. Typ. Max SOD2 10 t SOD4 10 t SOD8 ...
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... Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. * Note 1: High Impedance is measured by pulling to the appropriate rail with R CKo0-2 STo STo Figure 45 - Serial Output and External Control ZL50011 † - ST-BUS Output Tristate Timing Sym. Min. Typ. ...
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... Note 2: A delay of 600 microseconds must be applied before the first microprocessor access is performed after the RESET pin is set high CSD CS R/W A0-A11 D0-D15 READ D0-D15 WRITE DTA Figure 47 - Motorola Non-Multiplexed Bus Timing ZL50011 Sym. Min. Typ. Max CSS t 10 RWS t 5 ...
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... Reset pulse width † Characteristics are over recommended operating conditions unless otherwise stated. TCK t TMSS TMS t TDIS TDi TDo TRST Figure 48 - JTAG Test Port Timing Diagram Reset ZL50011 † - JTAG Test Port and Reset Pin Timing Sym. Min. t 100 TCKP t 80 TCKH t 80 ...
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... Zarlink Semiconductor 2002 All rights reserved. ISSUE ACN DATE APPRD. Package Code Previous package codes ...
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... Zarlink Semiconductor 2002 All rights reserved ISSUE 213834 ACN 213740 11Dec02 15Nov02 DATE APPRD. Package Code Previous package codes ...
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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...