zl50011 Zarlink Semiconductor, zl50011 Datasheet - Page 43

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zl50011

Manufacturer Part Number
zl50011
Description
Flexible 512 Channel Dx With On-chip Dpll
Manufacturer
Zarlink Semiconductor
Datasheet
5.2
The ZL50011 uses the public instructions defined in the IEEE 1149.1 standard. The JTAG Interface contains a
four-bit instruction register. Instructions are serially loaded into the instruction register from the TDI when the TAP
Controller is in its shifted-IR state. These instructions are subsequently decoded to achieve two basic functions: to
select the test data register that may operate while the instruction is current and to define the serial test data
register path that is used to shift data between TDI and TDO during data register scanning.
5.3
As specified in IEEE 1149.1, the ZL50011 JTAG Interface contains three test data registers:
5.4
A BSDL (Boundary Scan Description Language) file is available from Zarlink Semiconductor to aid in the use of the
IEEE 1149 test interface.
The Boundary-Scan Register - The Boundary-Scan register consists of a series of Boundary-Scan cells
arranged to form a scan path around the boundary of the ZL50011 core logic.
The Bypass Register - The Bypass register is a single stage shift register that provides a one-bit path from
TDI to its TDO.
The Device Identification Register - The JTAG device ID for the ZL50011 is 0C35B14B
Version<31:28>:
Part No. <27:12>:
Manufacturer ID<11:1>: 0001 0100 101
LSB<0>:
Instruction Register
Test Data Register
BSDL
0000
1
1100 0011 0101 1011
Zarlink Semiconductor Inc.
ZL50011
43
H
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Data Sheet

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