zl50011 Zarlink Semiconductor, zl50011 Datasheet - Page 40

• Manufacturer Part Number: zl50011
• Description: Flexible 512 Channel Dx With On-chip Dpll
• Manufacturer: Zarlink Semiconductor

ZL50011
Data Sheet
Although a short phase lock time is desirable, it is not always achievable due to other synchronizer requirements.
For instance, better jitter transfer performance is obtained with a lower frequency loop filter which increases lock
time; and better (smaller) phase slope performance (limiter) will increase lock time.
The DPLL loop filter and limiter have been optimized to meet the Telcordia GR-1244-CORE jitter transfer and
phase alignment speed requirements. If the frequency of the DPLL internal feedback signal is -50 ppm and the
frequency of the input reference is +50 ppm, then the phase lock time is typically 15 seconds. However, in a device
power up situation, phase lock time can be up to 50 seconds. The phase lock time meets Telcordia GR-1244-CORE
Stratum 4 requirements.
2.12
Alignment Between Input and Output Frame Pulses
When the device is in DPLL Master mode, and CKi/FPi is the selected input reference and has no jitter, then the
ST-BUS output frame pulses align very closely to the ST-BUS input frame pulse. See Figure 39 on page 72 for
details. (The alignment shown is for when all bits in the DPOA register are 0.) If the CKi/FPi reference has jitter, the
output frame pulses will still align to the input frame pulse but the offset value is a function of the input jitter.
When the device is in DPLL Master mode, and the selected input reference is not CKi/FPi, then the output frame
pulses have no relationship with respect to the input frame pulse. In this case, the device’s output frame pulse(s)
must be used as the frame pulse(s) for the system, which means that the output frame pulse(s) will be supplied as
the input frame pulse to all devices, including the device itself.
When the device is in DPLL Bypass Mode, the output frame pulses align closely to the input frame pulse. See
Figure 39 for details.
3.0
Oscillator Requirements
In DPLL Master and Freerun modes, the APLL module requires a 20 MHz clock source at the XTALi pin. The
20 MHz clock can be generated by connecting an external crystal oscillator to the XTALi and XTALo pins, or by
connecting an external clock oscillator to the XTALi pin.
If the device is to be used in DPLL Bypass mode only, external 20 MHz oscillator is not required, but the XTALi pin
should still get a valid clock signal so that the device can be initialized. The easiest way is to tie the CKi clock to the
XTALi pin. The XTALo pin must be left unconnected.
3.1
External Crystal Oscillator
A complete external crystal oscillator circuit made up of a crystal, resistor and capacitors is shown in Figure 30.
ZL50011
XTALi
20 MHz
1MΩ
56 pF
39 pF
3-50 pF
XTALo
100Ω
1uH
1uH inductor: may improve stability and is optional
Figure 30 - Crystal Oscillator Circuit
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Zarlink Semiconductor Inc.