zl50011 Zarlink Semiconductor, zl50011 Datasheet - Page 37

• Manufacturer Part Number: zl50011
• Description: Flexible 512 Channel Dx With On-chip Dpll
• Manufacturer: Zarlink Semiconductor

Divider - The Divider divides down the DCO output frequency. The following signals are generated:
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One of these signals is selected as the PLL feedback reference signal by the Frequency Select Mux circuit. The
clocks have 50% nominal duty cycle. FRAME is a 122 ns wide negative frame pulse. The duty cycle of the clocks
are not affected by the crystal oscillator duty cycle. Since these signals are generated from a common signal inside
the DPLL, the frame pulse and clock outputs are always locked to one another. They are also locked to the selected
input reference when the DPLL is in lock.
Frequency Select Mux - According to the selected input reference of the DPLL, this multiplexer will select the
appropriate divider output C2M, C1M5 or FRAME as the feedback signal in the PLL circuit.
2.11
The following are some synchronizer performance indicators and their definitions. The performance of the DPLL is
also indicated.
2.11.1
Intrinsic jitter is the jitter produced by a synchronizer and is measured at its output. It is measured by applying a
jitter free reference signal to the input of the device, and measuring its output jitter. Intrinsic jitter may also be
measured when the device is in a non-synchronizing mode, such as free running or holdover, by measuring the
output jitter of the device. Intrinsic jitter is usually measured with various band-limiting filters depending on the
applicable standards.
Intrinsic jitter is applicable only in Master and Freerun modes since in Bypass mode the DPLL is completely
bypassed.
The DPLL’s intrinsic jitter is 6.25 ns peak to peak. The intrinsic jitter will be added to the ST-BUS outputs CKo0-2,
FPo0-2, STo0-15 and STOHZ0-15. Since the DPLL master clock (MCKDPLL) comes from the on chip APLL which
is driven by the oscillator, any jitter on the oscillator will be added unattenuated onto the intrinsic jitter.
2.11.2
Jitter tolerance is a measure of the ability of a PLL to operate properly without cycle slips (i.e., remain in lock and/or
regain lock in the presence of large jitter magnitudes at various jitter frequencies) when jitter is applied to its
reference. The applied jitter magnitude and the jitter frequency depends on the applicable standards.
The DPLL’s jitter tolerance meets Telcordia GR-1244-CORE DS1 reference input jitter tolerance requirements.
2.11.3
Jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter
at the input of the device. Input jitter is applied at various amplitudes and frequencies, and output jitter is measured
with various filters depending on the applicable standards.
Since intrinsic jitter is always present, jitter attenuation will appear to be lower for small input jitter signals than for
large ones. Consequently, accurate jitter transfer function measurements are usually made with large input jitter
signals (e.g., 75% of the specified maximum jitter tolerance).
C2M (a 2.048 MHz clock)
C1M5 (a 1.544 MHz clock)
FRAME (an 8 kHz frame pulse)
DPLL Performance
Jitter Transfer
Intrinsic Jitter
DPLL Jitter Tolerance
Zarlink Semiconductor Inc.
ZL50011
37
Data Sheet