zl50011 Zarlink Semiconductor, zl50011 Datasheet - Page 42

• Manufacturer Part Number: zl50011
• Description: Flexible 512 Channel Dx With On-chip Dpll
• Manufacturer: Zarlink Semiconductor

4.0
The RESET pin is used to reset the device. When the pin is low, it synchronously puts the device in its reset state.
It disables the STo0 - 15 outputs, drives the STOHZ 0 - 15 outputs to high, clears the device registers and the
internal counters.
Upon power up, the device should be initialized as follows:
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5.0
The ZL50011 JTAG interface conforms to the Boundary-Scan IEEE1149.1 standard. The operation of the
boundary-scan circuitry is controlled by an external Test Access Port (TAP) Controller.
5.1
The Test Access Port (TAP) accesses the ZL50011 test functions. It consists of 3 input pins and 1 output pin as
follows:
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Set ODE pin to low to disable the STo0-15 output and to drive the STOHZ 0-15 to high.
Set the TRST pin to low to disable the JTAG TAP controller.
Reset the device by pulsing the RESET pin to low for longer than 1 ms.
After releasing the RESET pin from low to high, wait for 600µs for the APLL module and the crystal oscillator
to be stabilized before starting the first microprocessor port access cycle.
Program the register to define the frequency of the CKi input.
Wait for 600µs for the APLL module to be stabilized before starting the next microprocessor port access
cycle.
Configure the DPLL. After a device reset, the DPLL defaults are: Master mode, reference is REF pin input at
8 kHz, REF polarity is not inverted.
If DPLL Master mode is selected, wait 50 seconds for the DPLL to synchronize to the reference.
Use the memory block programming mode to initialize the connection memory.
Release the ODE pin to high after the connection memory is programmed such that bus contention will not
occur at the serial stream outputs STo0-15.
Test Clock Input (TCK) - TCK provides the clock for the test logic. The TCK does not interfere with any
on-chip clock and thus remains independent in the functional mode. The TCK permits shifting of test data
into or out of the Boundary-Scan register cells concurrently with the operation of the device and without
interfering with the on-chip logic.
Test Mode Select Input (TMS) - The TAP Controller uses the logic signals received at the TMS input to
control test operations. The TMS signals are sampled at the rising edge of the TCK pulse. This pin is
internally pulled to Vdd when it is not driven from an external source.
Test Data Input (TDi) - Serial input data applied to this port is fed either into the instruction register or into a
test data register, depending on the sequence previously applied to the TMS input. Both registers are
described in a subsequent section. The received input data is sampled at the rising edge of TCK pulses.
This pin is internally pulled to Vdd when it is not driven from an external source.
Test Data Output (TDo) - Depending on the sequence previously applied to the TMS input, the contents of
either the instruction register or data register are serially shifted out towards the TDO. The data out of the
TDO is clocked on the falling edge of the TCK pulses. When no data is shifted through the boundary scan
cells, the TDO driver is set to a high impedance state.
Test Reset (TRST) - Resets the JTAG scan structure. This pin is internally pulled to Vdd when it is not driven
from an external source.
Test Access Port (TAP)
Device Reset and Initialization
JTAG Support
Zarlink Semiconductor Inc.
ZL50011
42
Data Sheet