zl50011 Zarlink Semiconductor, zl50011 Datasheet - Page 27

• Manufacturer Part Number: zl50011
• Description: Flexible 512 Channel Dx With On-chip Dpll
• Manufacturer: Zarlink Semiconductor

2.4
To maintain the channel integrity in the constant delay mode, the usage of the input channel delay and output
channel delay modes affect the data delay through various switching paths due to additional data buffers. The
usage of these data buffers is enabled by the input and output channel delay bits (STIN#CD6-0 and STO#CD6-0) in
the Stream Input Delay and Stream Output Offset Registers. However, the input and output bit delay or the input
and output fractional bit offset have no impact on the overall data throughput delay.
In the following paragraphs, the data throughput delay (T) is expressed as a function of ST-BUS frames, input
channel number (m), output channel number (n), input channel delay (α) and output channel delay (β). Table 5
describes the variable range for input streams and Table 6 describes the variable range for output streams. Table 7
summarizes the data throughput delay under various input channel and output channel delay conditions.
Output Channel Delay OFF
Input Channel Delay OFF
Data Delay Through The Switching Paths
T = 2 frames + (n-m)
Input Stream
Data Rate
2 Mbps
4 Mbps
8 Mbps
Output Stream
Data Rate
2 Mbps
4 Mbps
8 Mbps
Output Channel Delay OFF
Table 6 - Variable Range for Output Streams
Input Channel Delay ON
Table 5 - Variable Range for Input Streams
T = 3 frames - α + (n-m)
Input Channel
Number (m)
Table 7 - Data Throughput Delay
0 to 127
0 to 31
0 to 63
Output Channel
Zarlink Semiconductor Inc.
Number (m)
0 to 127
0 to 31
0 to 63
ZL50011
27
Output Channel Delay ON
Input Channel Delay OFF
Possible Input channel delay (α)
T = 2 frames + β + (n-m)
Possible Output channel
1 to 127
1 to 31
1 to 63
delay (β)
1 to 127
1 to 31
1 to 63
Output Channel Delay ON
T= 3 frames - α + β + (n-m)
Input Channel Delay ON
Data Sheet